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公开(公告)号：US09927486B2
公开(公告)日：2018-03-27
申请号：US15241805
申请日：2016-08-19
发明人： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
IPC分类号： G06F12/00 , G11C7/00 , G01R31/28 , G01R31/317 , G06F21/44 , G06F21/62 , G06F21/85 , G06F11/34
CPC分类号： G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
摘要： Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US09898625B2
公开(公告)日：2018-02-20
申请号：US14727299
申请日：2015-06-01
IPC分类号： G01R11/24 , G06F21/81 , G06F1/28 , G06F1/14 , G01R31/317
CPC分类号： G06F21/81 , G01R31/31719 , G06F1/14 , G06F1/28
摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
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公开(公告)号：US09891277B2
公开(公告)日：2018-02-13
申请号：US14502406
申请日：2014-09-30
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/31719 , G01R31/31701
摘要： An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.
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公开(公告)号：US20180004944A1
公开(公告)日：2018-01-04
申请号：US15543501
申请日：2016-01-12
CPC分类号： G06F21/556 , G01R31/2884 , G01R31/31719 , G06F11/22 , H01L21/822 , H01L27/04 , H04L9/10
摘要： Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented.
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15.发明申请公开(公告)号：US20170244549A1
公开(公告)日：2017-08-24
申请号：US15439578
申请日：2017-02-22
申请人： ESHARD
IPC分类号： H04L9/00
CPC分类号： H04L9/003 , G01R31/31719 , G06F21/72 , G06F21/75 , G09C1/00 , H04L9/002 , H04L9/3242 , H04L9/3247 , H04L9/3249 , H04L9/3252 , H04L2209/08 , H04L2209/12
摘要： A test method for a circuit can include: acquiring a plurality of value sets including values corresponding to activity of the circuit when the circuit executes an operation of an operation set of distinct cryptographic operations applied to a same secret data, selecting at least two subsets of values in each value set, for each value set and each value subset, counting occurrence numbers of values transformed by a respective first surjective function applied to the values of the subset, for each value set, forming all possible n-tuples associating together one of the occurrence numbers of each value subset of the value set, and computing a combined occurrence number for each n-tuple of the value set by multiplying together the occurrence numbers associated by the n-tuple, to form an occurrence number set for the value set, for each operation of the operation set, and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets, obtained by adding together the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the secret data part, provide a partial operation result having a same transformed value by a second surjective function, and analyzing the cumulative occurrence number sets to determine the part of the secret data.
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16.发明申请公开(公告)号：US20170160320A1
公开(公告)日：2017-06-08
申请号：US15368273
申请日：2016-12-02
IPC分类号： G01R23/02
CPC分类号： G01R23/02 , G01R29/0814 , G01R31/31719
摘要： Some embodiments described herein include an apparatus having a memory and a processor operatively coupled to the memory. The processor is configured to receive, in response to an excitation signal and from the power signature detector, a power signature signal associated with a target electronic device disposed within a sealed package. The processor is configured to extract a characteristic of the power signature signal and compare the characteristic of the power signature signal with a characteristic of a reference power signature signal associated with at least one reference device to determine a counterfeit status of the target electronic device. The at least one reference device is a pre-determined trusted device or a pre-determined counterfeit device. The processor is configured to send, to a communication interface, a notification signal associated with the counterfeit status of the target electronic device.
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公开(公告)号：US20170141930A1
公开(公告)日：2017-05-18
申请号：US15353412
申请日：2016-11-16
IPC分类号： H04L9/32 , G06F21/70 , H04L9/06 , G01R31/317
CPC分类号： H04L9/3278 , G01R31/31719 , G01R31/318588 , G06F21/75 , H04L9/0662 , H04L2209/12
摘要： Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.
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公开(公告)号：US09606167B2
公开(公告)日：2017-03-28
申请号：US13565420
申请日：2012-08-02
申请人： Hsiang-Tsung Kung , Dario Vlah
发明人： Hsiang-Tsung Kung , Dario Vlah
IPC分类号： G01R31/26 , G06F11/07 , G01R31/3183 , G01R31/317
CPC分类号： G01R31/2601 , G01R31/31719 , G01R31/31721 , G01R31/31835 , G06F11/0751
摘要： Circuitry, systems and methods for testing integrated circuits for the presence of anomalies. Techniques include applying a plurality of inputs to an integrated circuit under test to obtain a first plurality of measurements at least partially characterizing power leakage in the integrated circuit under test, encode the first plurality of measurements, by computing a plurality of random linear combinations of measurements in the first plurality of measurements, to obtain a second plurality of encoded measurements determining whether the integrated circuit under test contains at least one anomaly based, at least in part, on the second plurality of encoded measurements.
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公开(公告)号：US20170063821A1
公开(公告)日：2017-03-02
申请号：US14851429
申请日：2015-09-11
CPC分类号： H04L63/08 , G01R31/31719 , G09C1/00 , H04L9/0866 , H04L9/3234 , H04L9/3278 , H04L2209/26
摘要： This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint code having an encoded version of a private value generated by the security circuitry—for transmission to the security server. The security circuitry can authenticate the integrated circuit by replying to a request to verify authentication of the integrated circuit from the security server. The response can confirm to the security server that the integrated circuit includes the private value, which can authenticate the integrated circuit.
摘要翻译： 本申请公开了一种供应链安全技术，其向安全服务器注册集成电路，并随后利用该注册来验证集成电路。 集成电路可以包括安全电路，以通过生成注册消息（包括具有由安全电路产生的私有值的编码版本的指纹码）的注册消息来向安全服务器注册集成电路 - 以传输到安全服务器。 安全电路可以通过回答从安全服务器验证集成电路的认证的请求来认证集成电路。 响应可以向安全服务器确认集成电路包括可以验证集成电路的私有值。
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公开(公告)号：US09506981B2
公开(公告)日：2016-11-29
申请号：US14816453
申请日：2015-08-03
发明人： Fabrice Walter
IPC分类号： G01R31/317 , G06F21/55 , G06F21/75 , H03K19/003
CPC分类号： G01R31/31727 , G01R31/31719 , G06F21/554 , G06F21/75 , H03K19/003
摘要： A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.
摘要翻译： 用于安全应用的电路配置包括在集成电路的关键点处以数字单元布置的几个内部频率检测器。 时钟检测器被隐藏在集成电路的数字部分中，每个作为标准单元（触发器单元），以防止任何外部操作并且隐藏其功能。 时钟检测器优选地设置在时钟树拓扑中，时钟树拓扑可以处于几个级别，用于在关键点通过不同的数字单元树分发时钟信号。 如果在任何级别监视了外部时钟攻击，则通过时钟检测器网络生成报警。
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