公开(公告)号：US06171908B2

公开(公告)日：2001-01-09

申请号：US09123585

申请日：1998-07-28

申请人： Bin-Shing Chen

发明人： Bin-Shing Chen

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7886

摘要： A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

摘要翻译： 一种用于形成具有自对准栅极层的集成电路器件的技术。 该方法包括各种步骤，例如提供通常是硅晶片的衬底（217）。 在半导体衬底中限定包括第一隔离区域和第二隔离区域的场隔离区域（201）。 在第一隔离区域和第二隔离区域之间限定凹陷区域。 隔离区域（201）使用通常称为LOCOS的硅工艺的局部氧化制成，但可以是其它的。 材料（205）如多晶硅的厚度沉积在第一隔离区域，第二隔离区域和有源区域上。 执行选择性地去除覆盖第一隔离区域和第二隔离区域的部分的厚度的部分的步骤，其中去除步骤在凹陷区域中形成基本平坦的材料区域。 使用去除步骤，基本平坦的材料区域自对准到凹陷区域。

公开(公告)号：US5793080A

公开(公告)日：1998-08-11

申请号：US718224

申请日：1996-09-20

申请人： Hyun Sang Hwang

发明人： Hyun Sang Hwang

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7886

摘要： A nonvolatile memory device includes a semiconductor substrate of a first conductivity type; a gate insulating film formed on the substrate; a floating gate having a first region and a second region, the first region lying flat over the gate insulating film and the second region being extended from a first end portion of the first region and perpendicular to the first region; a control gate extending parallel to the second region of the floating gate, lying over the second end portion of the first region of the floating gate and perpendicular to the first region; an inter-insulating layer disposed between the floating gate and the control gate; a first spacer formed at a side wall of the second region of the floating gate and a second spacer formed at a side wall defined by the floating gate and the control gate; a high density source region of a second conductivity type formed in the substrate, being disposed a thickness of the first spacer distant from the floating gate; a first high density drain region of the second conductivity type formed in the substrate, underlapping the floating gate; and a second high density drain region of the second conductivity type formed in the substrate, being disposed a thickness of the second spacer distant from the floating gate and adjacent to the first high density drain region.

摘要翻译： 非易失性存储器件包括第一导电类型的半导体衬底; 形成在基板上的栅极绝缘膜; 具有第一区域和第二区域的浮动栅极，所述第一区域平坦地覆盖所述栅极绝缘膜，并且所述第二区域从所述第一区域的第一端部延伸并垂直于所述第一区域; 平行于所述浮动栅极的所述第二区域延伸的控制栅极，位于所述浮置栅极的所述第一区域的第二端部并且垂直于所述第一区域; 设置在所述浮动栅极和所述控制栅极之间的绝缘层; 形成在浮置栅极的第二区域的侧壁处的第一间隔物和形成在由浮动栅极和控制栅极限定的侧壁处的第二间隔物; 形成在所述基板中的第二导电类型的高密度源区，设置所述第一隔离物与所述浮动栅极远离的厚度; 形成在衬底中的第二导电类型的第一高密度漏极区，使浮置栅极重叠; 以及形成在所述基板中的所述第二导电类型的第二高密度漏极区域，所述第二高密度漏极区域布置成远离所述浮置栅极并且邻近所述第一高密度漏极区域的所述第二隔离物的厚度。

公开(公告)号：US5646430A

公开(公告)日：1997-07-08

申请号：US520350

申请日：1995-08-28

申请人： Cetin Kaya ,  David Liu

发明人： Cetin Kaya ,  David Liu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/7886

摘要： In one embodiment, a non-volatile memory structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region. 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

摘要翻译： 在一个实施例中，非易失性存储器结构10包括形成在半导体衬底8的表面中并被沟道区分隔开的重掺杂源极11和漏极12区域。 浮动栅极13形成在沟道区域21的上方并与沟道区域21绝缘，并且控制栅极14形成在浮置栅极13之上并与浮动栅极13绝缘。轻掺杂区域20形成在浮动栅极13下方的沟道21中并且邻接 源区域11.轻掺杂区域20与所述衬底8的表面间隔开。还公开了其它实施例和工艺。

公开(公告)号：US5455793A

公开(公告)日：1995-10-03

申请号：US340810

申请日：1994-11-17

申请人： Alaaeldin A. M. Amin ,  James Brennan, Jr.

发明人： Alaaeldin A. M. Amin ,  James Brennan, Jr.

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L29/7886 ,  G11C16/0425

摘要： A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor. A memory cell structure described in accordance with this invention allows a reduction of the portion of the floating gate covering the programmable transistor portion of the channel length. This results in a reduction in the floating gate to substrate capacitance (C.sub.FB) thereby improving the programming coupling ratio and reducing the overall cell size.

摘要翻译： 使用具有两个或三个多晶硅层技术的具有两个独立N +注入的非自对准CMOS工艺提供了一种新颖的非易失性存储单元结构，其允许在电池电擦除和重新编程以及减小单元尺寸要求。 新颖的存储器单元由具有存取晶体管和可编程晶体管的合并晶体管结构来实现。 存储单元通过具有由第一多晶硅层形成的控制栅极构成，该第一多晶硅层覆盖漏极和源极之间的沟道长度的一部分以形成合并晶体管的存取部分，以及由第二多晶硅层重叠形成的浮置栅极 沟道长度的第二部分，以形成合并晶体管的可编程晶体管部分。 这种合并的晶体管结构相当于串联的两个晶体管，一个与存取晶体管串联的可编程晶体管。 根据本发明描述的存储单元结构允许减少覆盖通道长度的可编程晶体管部分的浮动栅极的部分。 这导致浮栅对基极电容（CFB）的降低，从而提高编程耦合比并降低整体单元尺寸。

公开(公告)号：US5189497A

公开(公告)日：1993-02-23

申请号：US765065

申请日：1991-09-24

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/105 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US5101249A

公开(公告)日：1992-03-31

申请号：US859237

申请日：1986-05-06

申请人： Shinpei Hijiya ,  Takao Nozaki ,  Takashi Ito ,  Hajime Ishikawa

发明人： Shinpei Hijiya ,  Takao Nozaki ,  Takashi Ito ,  Hajime Ishikawa

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886

摘要： A nonvolatile semiconductor memory device comprising: a substrate, a pair of source and drain regions; a channel region between the source and drain regions; a pair of first and second insulating layers on the channel region, and a floating-gate or traps between the first and second insulating layer. The band gap of the first insulating layer increases gradually from the substrate to the floating gate or the traps.

摘要翻译： 一种非易失性半导体存储器件，包括：衬底，一对源极和漏极区; 源区和漏区之间的沟道区; 沟道区域上的一对第一和第二绝缘层，以及在第一和第二绝缘层之间的浮栅或阱。 第一绝缘层的带隙从衬底到浮栅或陷阱逐渐增加。

公开(公告)号：US4503519A

公开(公告)日：1985-03-05

申请号：US359706

申请日：1982-03-19

申请人： Hideki Arakawa

发明人： Hideki Arakawa

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： H01L29/7886

摘要： A semiconductor non-volatile memory element of an electrically erasable type includes a floating gate formed on a semiconductor substrate through a first insulating film, and an erase-only or a write/erase gate formed through a second insulating film on the floating gate. The second insulating film is an oxidized film formed by thermal oxidation of polycrystalline silicon having a thickness in the range between 150 and 400 angstroms. Due to such a thin insulating film, the amount of electrons trapped in the second insulating film is greatly decreased so that erasure is possible a greater number of times.

摘要翻译： 电可擦除型的半导体非易失性存储元件包括通过第一绝缘膜形成在半导体衬底上的浮动栅极，以及通过浮置栅极上的第二绝缘膜形成的仅擦写或写/擦除栅极。 第二绝缘膜是通过多晶硅的热氧化而形成的氧化膜，其厚度在150-400埃的范围内。 由于这种薄的绝缘膜，被捕获在第二绝缘膜中的电子的量大大降低，从而可以进行更多次的擦除。

公开(公告)号：US4222063A

公开(公告)日：1980-09-09

申请号：US910789

申请日：1978-05-30

申请人： Thurman J. Rodgers

发明人： Thurman J. Rodgers

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L27/10 ,  G11C11/40

CPC分类号： H01L29/7886 ,  G11C16/0416 ,  Y10S257/927

摘要： A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

摘要翻译： 半导体电可编程只读存储器件（EPROM）利用单个V型MOSFET形式的存储器单元阵列，其使用阈值逻辑的电容耦合版本来实现正常的与功能（数据字地址）。 每个MOSFET由位于每个位线和字线的交叉点处的V形凹槽形成，该位线延伸穿过扩散位线（其用作晶体管漏极）并进入衬底（其用作源极和接地平面 装置）。 类似的V形浮动栅极通过薄氧化物层隔离交叉位和字线的下方和上方。 围绕每个V形凹槽的上端并与其周围的N型漏极区相邻的P型导电材料环用于降低所需的编程电压而不增加器件阈值电压。

公开(公告)号：US4043024A

公开(公告)日：1977-08-23

申请号：US634187

申请日：1975-11-21

申请人： Seiichi Iwamatsu

发明人： Seiichi Iwamatsu

IPC分类号： H01L21/265 ,  D04B9/00 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  B01J17/00

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/31155 ,  H01L29/7886 ,  Y10S148/082

摘要： A method of manufacturing a semiconductor storage device comprises the steps of forming a source region and a drain region in a surface of a semiconductor substrate of a first conductivity type in a manner to be spaced from each other, said source and drain regions having a second conductivity type; forming an insulating film on said semiconductor substrate between said source and drain regions; implanting ions of an electrically conductive element into said insulating film, to thus form a floating gate; and leading out source and drain electrodes from said source and drain regions, respectively. By varying the implantation energy and the implantation dose rate in the implanting step, the amount of charges to be accumulated in the floating gate can be controlled.

摘要翻译： 一种制造半导体存储装置的方法包括以下步骤：在第一导电类型的半导体衬底的表面中以彼此间隔开的方式形成源极区域和漏极区域，所述源极和漏极区域具有第二 导电型; 在所述源区和漏区之间的所述半导体衬底上形成绝缘膜; 将导电元件的离子注入到所述绝缘膜中，从而形成浮栅; 并分别从所述源极和漏极区域引出源极和漏极。 通过改变注入步骤中的注入能量和注入剂量率，可以控制在浮动栅极中积聚的电荷量。

公开(公告)号：US4035820A

公开(公告)日：1977-07-12

申请号：US644983

申请日：1975-12-29

申请人： Walter Theodore Matzen

发明人： Walter Theodore Matzen

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34 ,  H01L29/90

CPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L29/7886 ,  Y10S148/136

摘要： A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

摘要翻译： 已经制造了双注入器，浮栅MOS非易失性半导体存储器件（DIFMOS），其中电子注入装置包括通过离子注入控制的具有临界掺杂剂浓度的p + n +结。 接点被雪崩以在浮动栅极上“写入”一个电荷，并且空穴注入器结（n + / p-）被雪崩以“擦除”电荷。 其栅极是浮动栅极的延伸的MOS感测晶体管“读取”在浮动栅极上存在或不存在电荷。 在优选实施例中，空穴注入装置包括用于将电压偏压耦合到浮动栅极的MOS“自举”电容器。