公开(公告)号：US5340760A

公开(公告)日：1994-08-23

申请号：US992473

申请日：1992-12-15

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： A01H5/02 ,  H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/335

CPC分类号： A01H5/02 ,  H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5079603A

公开(公告)日：1992-01-07

申请号：US517386

申请日：1990-04-30

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886 ,  H01L27/105 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US5189497A

公开(公告)日：1993-02-23

申请号：US765065

申请日：1991-09-24

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/105 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US5604142A

公开(公告)日：1997-02-18

申请号：US419232

申请日：1995-04-10

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5472891A

公开(公告)日：1995-12-05

申请号：US260229

申请日：1994-06-14

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

CPC分类号： H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并且采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US4633438A

公开(公告)日：1986-12-30

申请号：US681027

申请日：1984-12-13

申请人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

发明人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

IPC分类号： G11C11/405 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/405 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108

摘要： In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

摘要翻译： 在用于动态操作的3晶体管随机存取存储器中，本发明公开了一种晶体管中的一个堆叠在另一个晶体管上的结构。 用于写入的晶体管设置在用于读取的晶体管上，并且其一个端子与用于判断数据的晶体管的栅电极共同使用。 另一个端子连接到晶体管的一个端子用于读取。 可以获得能够进行极大规模集成的存储单元。

公开(公告)号：US5097446A

公开(公告)日：1992-03-17

申请号：US355480

申请日：1989-05-23

申请人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

发明人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

IPC分类号： G11C16/32 ,  G11C16/34

CPC分类号： G11C16/3477 ,  G11C16/32 ,  G11C16/3468 ,  G11C16/3486

摘要： A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.

摘要翻译： 提供了一种用于可电气写入的非易失性存储器件的时间电路。 当从外部设备指定对特定存储单元持续相当长时间段的写入操作时，无论外部写入操作规范如何，当定时器上设置的时间时，存储器件停止该存储器单元上的写入操作 电路已经过去了 非易失性存储器件具有各自由单个晶体管组成的存储单元。 根据流过这些存储单元的电流来控制对存储单元的擦除操作。

公开(公告)号：US4443718A

公开(公告)日：1984-04-17

申请号：US188740

申请日：1980-09-19

申请人： Takaaki Hagiwara ,  Yuji Yatsuda

发明人： Takaaki Hagiwara ,  Yuji Yatsuda

IPC分类号： H01L27/112 ,  G11C11/41 ,  G11C16/06 ,  G11C16/26 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H03K19/0185 ,  H03K19/0944 ,  G11C7/06 ,  G11C11/40

CPC分类号： H03K19/09443 ,  G11C16/26 ,  H03K19/018507

摘要： A nonvolatile semiconductor memory including a memory matrix having a plurality of memory cells with nonvolatile memory elements and arranged in the form of a matrix, a selecting circuit for selecting a desired memory cell from the memory matrix, and a read-out circuit for reading out the information stored in the selected memory cell. The read-out circuit includes a sense amplifier and an output buffer. The sensed amplifier includes an inverter having a load element to which a supply voltage is applied and a selected memory cell acting as a driver element. The output buffer includes a level shift circuit for shifting the level of an output signal voltage from the sense amplifier with the level shift circuit including a stabilizing circuit for stabilizing the level of the shifted signal voltage during fluctuations in the supply voltage. An output driver circuit is provided for receiving the shifted signal voltage from the level shift circuit.

摘要翻译： 一种非易失性半导体存储器，包括具有多个具有非易失性存储元件的存储单元并以矩阵形式布置的存储器矩阵，用于从存储矩阵中选择所需存储单元的选择电路和用于读出的读出电路 存储在所选存储单元中的信息。 读出电路包括读出放大器和输出缓冲器。 感测的放大器包括具有施加电源电压的负载元件和用作驱动器元件的选择的存储器单元的逆变器。 输出缓冲器包括电平移位电路，用于通过电平移位电路来移位来自读出放大器的输出信号电压的电平，该电平移位电路包括用于在电源电压波动期间稳定移位信号电压电平的稳定电路。 提供一个输出驱动器电路，用于接收来自电平移位电路的移位信号电压。

公开(公告)号：US4264376A

公开(公告)日：1981-04-28

申请号：US66795

申请日：1979-08-15

申请人： Yuji Yatsuda ,  Shinichi Minami ,  Ryuji Kondo ,  Takaaki Hagiwara ,  Yokichi Itoh

发明人： Yuji Yatsuda ,  Shinichi Minami ,  Ryuji Kondo ,  Takaaki Hagiwara ,  Yokichi Itoh

IPC分类号： H01L27/112 ,  G11C16/04 ,  H01L21/28 ,  H01L21/30 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/324

CPC分类号： H01L21/28185 ,  G11C16/0466 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792 ,  Y10S438/909

摘要： A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.

摘要翻译： 公开了一种金属 - 氮化硅 - 氧化硅 - 衬底（MNOS）型非易失性存储器件。 在形成氮化硅膜之后，进行氢气氛中的热处理。 作为这种热处理的结果，防止存储器保持特性的劣化，从而可以获得与具有铝栅极的常规非易失性存储器件相当的具有硅栅极的非易失性存储器件。