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公开(公告)号：US20170077918A1
公开(公告)日：2017-03-16
申请号：US14855238
申请日：2015-09-15
发明人： Neha Agrawal , Sajin Mohamad , Chulkyu Lee
CPC分类号： H03K7/06 , G06F1/08 , H03K3/037 , H03K19/21 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/64
摘要： Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.
摘要翻译： 通过可编程分频比对输入时钟信号进行分频的系统和方法可以产生输出时钟信号，输出时钟信号与输入时钟信号的延迟无关于分频比的值，输出时钟信号的占空比为50 ％独立于分频比的值。 示例性可编程时钟分频器包括模N计数器，其产生计数分频比的计数信号和产生公共半速率时钟信号的半速率时钟信号发生器，偶数半速率时钟信号和奇数 半速率时钟信号以输出时钟信号的一半速率切换。 公共半速时钟信号，偶数半速率时钟信号和奇数半速率时钟信号被组合以产生输出时钟信号。
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12.发明授权公开(公告)号：US09246494B2
公开(公告)日：2016-01-26
申请号：US14135554
申请日：2013-12-19
发明人： Marty Pflum
CPC分类号： H03K21/10 , B65H2220/01 , B65H2513/11 , B67D7/228 , G01R23/10 , H03K5/1532 , H03K23/64
摘要： A method includes receiving a count corresponding to a number of peaks of a resonant signal that exceed a reference signal and comparing the count to a floating count window defined by a first count threshold and a second count threshold, the first count threshold is larger than the second count threshold. The method further includes selectively shifting the floating count window in a direction of the count when the count falls outside of the floating count window.
摘要翻译： 一种方法包括接收对应于超过参考信号的谐振信号的峰值数量的计数，并将计数与由第一计数阈值和第二计数阈值定义的浮动计数窗口进行比较，第一计数阈值大于 第二计数阈值。 该方法还包括当计数落在浮动计数窗口之外时，在计数方向上选择性地移动浮动计数窗口。
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13.发明申请公开(公告)号：US20150180479A1
公开(公告)日：2015-06-25
申请号：US14135554
申请日：2013-12-19
发明人： Marty Pflum
CPC分类号： H03K21/10 , B65H2220/01 , B65H2513/11 , B67D7/228 , G01R23/10 , H03K5/1532 , H03K23/64
摘要： A method includes receiving a count corresponding to a number of peaks of a resonant signal that exceed a reference signal and comparing the count to a floating count window defined by a first count threshold and a second count threshold, the first count threshold is larger than the second count threshold. The method further includes selectively shifting the floating count window in a direction of the count when the count falls outside of the floating count window.
摘要翻译： 一种方法包括接收对应于超过参考信号的谐振信号的峰值数量的计数，并将计数与由第一计数阈值和第二计数阈值定义的浮动计数窗口进行比较，第一计数阈值大于 第二计数阈值。 该方法还包括当计数落在浮动计数窗口之外时，在计数方向上选择性地移动浮动计数窗口。
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公开(公告)号：US07187217B2
公开(公告)日：2007-03-06
申请号：US11060477
申请日：2005-02-18
申请人： Masazumi Marutani
发明人： Masazumi Marutani
摘要： A clock frequency divider is provided which has first through Pth (where P is an integer) sub-counters, each capable of counting M+1 clock pulses and provided in parallel, and first through Pth clock signals are provided to the sub-counters, which has same period as a reference clock signal and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first through Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.
摘要翻译： 提供了具有第一到第P（其中P是整数）子计数器的时钟分频器，每个子计数器能够对M + 1个时钟脉冲进行并行并行并行提供，并且第一到第P个时钟信号被提供给子计数器， 其与参考时钟信号具有相同的周期，并且被顺序地移动参考时钟信号的周期的1 / P。 在第一到第P子计数器中，当第N个子计数器（其中N是从1到P的任意数字）完成计数指定数量M的参考时钟脉冲时，所有其他子计数器被初始化，或者在 至少第（N + 1）个子计数器被初始化。
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