公开(公告)号：US5896101A

公开(公告)日：1999-04-20

申请号：US710371

申请日：1996-09-16

申请人： John Laurence Melanson

发明人： John Laurence Melanson

IPC分类号： G01S19/21 ,  H03M1/12 ,  H03M3/04 ,  H03M3/02

CPC分类号： H03M3/388 ,  H03M3/424 ,  H03M3/454

摘要： In a delta sigma modulator, generally comprising one or more integrators fed into a multilevel quantizer, the output of which is the output of the delta sigma modulator and is also fed through a digital to analog converter in a feedback loop to the integrators, the quantizer is made sparse, i.e. the levels output by the quantizer are not evenly spaced, but rather are closely spaced for small deviations from 0 V, and broadly spaced for large deviations from 0V. The A/D converter in the feedback is matched to the quantizer. For example, the levels might be -1 V, -1/8 V, 0V, 1/8 V, and 1 V. The digital output signal from the sparse quantizer is fed into a correction RAM, which corrects for nonlinearities in the D/A converter before the digital signal is filtered by a low pass filter and frequency down converted. The contents of the RAM are selected whenever the A/D conversion system is powered on. The contents of the RAM are selected by closing a series of sets switches in the A/D converter and adjusting the output of the RAM to 0.

摘要翻译： 在ΔΣ调制器中，通常包括馈送到多电平量化器中的一个或多个积分器，其输出是ΔΣ调制器的输出，并且还通过反馈回路中的数模转换器馈送到积分器，量化器 是稀疏的，即由量化器输出的电平不是均匀间隔的，而是与0V的小偏差紧密隔开，并且与0V的大偏差大致间隔开。 反馈中的A / D转换器与量化器匹配。 例如，电平可能是-1V，-1 / 8V，0V，1/8V和1V。来自稀疏量化器的数字输出信号被馈送到校正RAM中，其校正D中的非线性 / A转换器之前，数字信号被低通滤波器滤波并降频转换。 只要A / D转换系统上电，RAM内容就会被选中。 通过关闭A / D转换器中的一系列开关并将RAM的输出调整为0来选择RAM的内容。

公开(公告)号：US5781138A

公开(公告)日：1998-07-14

申请号：US772785

申请日：1996-12-23

申请人： Niels Knudsen

发明人： Niels Knudsen

IPC分类号： H03M3/02 ,  H03M1/06

CPC分类号： H03M3/388 ,  H03M3/424 ,  H03M3/458

摘要： A system and method for reducing linearity errors in a delta-sigma converter. The linearity errors in the delta-sigma converter are modeled by generating a set of digital signals representative of an inputted sine wave. The set of digital signals are low-pass filtered and subjected to a fast Fourier transform algorithm to generate a frequency domain representation of the sine wave. Thereafter, a net linearity error spectrum is removed from the frequency domain representation and inverse Fourier transform back into the time domain. The filtered set of digital signals are also sorted into subsets of digital signals where each signal in a subset corresponds to a particular output of a delta-sigma modulator contained within the delta-sigma converter. A fast Fourier transform algorithm is applied to each of the filtered subsets of digital signals to generate a frequency domain representation thereof. Specific linearity errors are generated by applying an inverse Fourier transform algorithm to each of the specific linearity error spectrums in the frequency domain representations of the filtered subsets of digital signals. Thereafter, linearity error correction coefficients are generated as a function of the net linearity error and the specific linearity errors. The linearity error correction coefficients are used to generate entries in a look-up table where the entries are adjustable by digital outputs of the delta-sigma modulator. The look-up table is used to correct digital signals outputted by the delta-sigma modulator prior to decimation and digital filter.

摘要翻译： 用于减小Δ-Σ转换器中的线性误差的系统和方法。 Δ-Σ转换器中的线性误差通过产生代表​​输入的正弦波的一组数字信号来建模。 该组数字信号被低通滤波并经受快速傅立叶变换算法以产生正弦波的频域表示。 此后，将净线性误差谱从频域表示和逆傅里叶变换中移除回时域。 经滤波的数字信号组也被分类为数字信号的子集，其中子集中的每个信号对应于包含在Δ-Σ转换器内的Δ-Σ调制器的特定输出。 快速傅立叶变换算法被应用于数字信号的滤波子集中的每一个以产生其频域表示。 通过对经过滤波的数字信号子集的频域表示中的每个特定线性误差谱应用逆傅里叶变换算法来产生特定的线性误差。 此后，产生线性误差校正系数作为净线性误差和特定线性误差的函数。 线性误差校正系数用于在查询表中生成条目，其中条目可由delta-Σ调制器的数字输出调节。 查找表用于在抽取和数字滤波之前校正由Δ-Σ调制器输出的数字信号。

公开(公告)号：US5682160A

公开(公告)日：1997-10-28

申请号：US650282

申请日：1996-05-20

申请人： David Byrd Ribner ,  David Henry Kenneth Hoe

发明人： David Byrd Ribner ,  David Henry Kenneth Hoe

IPC分类号： H03M3/04 ,  H03M3/02

CPC分类号： H03M3/374 ,  H03M3/388 ,  H03M3/424 ,  H03M3/454

摘要： A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.

摘要翻译： 一个ΔΣ调制器使得每个级联积分器能够在一个完整的时钟周期内独立地稳定，并且使用反馈路径中的二项式系数来获得所需的量化器误差的正弦整形，实现了采样率和阶数的提高以提高分辨率。 使用多位量化器也可以提高调制器分辨率。 在一个实施例中，调制器包括多个级联的单位延迟积分器，并在反馈回路中利用二项式系数缩放。 多位模数转换器被耦合以接收级联单元延迟积分器的输出信号。 反馈回路包括耦合到多位模数转换器的输出的多位数模转换器。 数模转换器的输出耦合到至少第一和第二差分求和结的输入端。

公开(公告)号：US5341135A

公开(公告)日：1994-08-23

申请号：US876781

申请日：1992-04-30

申请人： Timothy H. B. Pearce

发明人： Timothy H. B. Pearce

IPC分类号： H03M3/02 ,  H03M7/00 ,  H03M1/10

CPC分类号： H03M7/3006 ,  H03M3/414 ,  H03M3/388 ,  H03M7/3022

摘要： An analog-to-digital converter includes a filter having an input for receiving, via a summing node, a signal derived from the analog input signal. A first quantizer produces a first digital signal from a signal derived from the output of the filter. A feedback loop feeds a signal derived from the first digital signal to be combined in analog form with the signal derived from the analog input signal at the summing node, so that the filter in use receives an error signal representing the difference between the signal derived from the analog input signal and the analog representation of the first digital signal. An error signal filter filters the error signal to remove noise outside the passband of the analog-to-digital converter. A second quantizer produces a second digital signal representative of the filtered error signal, and a combining circuitry combines the first and second digital signals to produce a digital output signal representative of the analog input signal.

摘要翻译： 模数转换器包括具有用于经由求和节点从模拟输入信号导出的信号的输入的滤波器。 第一量化器根据从滤波器的输出得到的信号产生第一数字信号。 反馈回路馈送来自第一数字信号的信号，以与模拟输入信号在求和节点处的模拟信号相组合，使得使用的滤波器接收到一个误差信号，该误差信号表示从 模拟输入信号和第一数字信号的模拟表示。 误差信号滤波器滤除误差信号以去除模数转换器通带外的噪声。 第二量化器产生表示经滤波的误差信号的第二数字信号，并且组合电路组合第一和第二数字信号以产生表示模拟输入信号的数字输出信号。

公开(公告)号：US20180302102A1

公开(公告)日：2018-10-18

申请号：US15900598

申请日：2018-02-20

申请人： Renesas Electronics Corporation

发明人： Takashi OSHIMA ,  Tetsuo MATSUI ,  Mitsuya FUKAZAWA ,  Tomohiko YANO

IPC分类号： H03M3/00 ,  H03H21/00 ,  G01S13/02 ,  G01S7/35

CPC分类号： H03M3/414 ,  G01S7/354 ,  G01S13/0209 ,  H03H21/0012 ,  H03M3/38 ,  H03M3/388 ,  H03M3/458

摘要： A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.

公开(公告)号：US09343052B2

公开(公告)日：2016-05-17

申请号：US14661410

申请日：2015-03-18

申请人： CASIO COMPUTER CO., LTD.

发明人： Goro Sakata

IPC分类号： G10H1/06 ,  G10H1/34 ,  H03M3/00 ,  G10H7/00

CPC分类号： G10H1/34 ,  G10H7/002 ,  G10H2240/071 ,  G10H2250/545 ,  H03M3/388 ,  H03M3/506

摘要： In the present embodiment, quantizer output values including variation values corresponding to duty errors of pulse width data (PWM output signals) occurring by the difference of the pull-down/pull-up drive characteristics (drive capabilities) of a buffer are stored in advance in a feedback value memory in a quantizer as feedback values FBV0 to FBV4, and a feedback value FBVn read out from the feedback value memory in response to the quantization of a delta-sigma modulation output is inputted into a subtractor by return input. Then, a quantizer output value including a variation value corresponding to a duty error is subtracted from input data Din, and delta-sigma modulation is performed such that the difference is minimized, whereby the duty error of pulse width data (PWM output signal) is compensated.

摘要翻译： 在本实施例中，预先存储包括由缓冲器的下拉/上拉驱动特性（驱动能力）的差引起的脉冲宽度数据（PWM输出信号）的占空比误差对应的量化器输出值 在量化器中的反馈值存储器中作为反馈值FBV0至FBV4，并且响应于Δ-Σ调制输出的量化从反馈值存储器读出的反馈值FBVn通过返回输入被输入减法器。 然后，从输入数据Din中减去包括与占空比误差对应的变化值的量化器输出值，进行Δ-Σ调制使差值最小化，由此脉冲宽度数据（PWM输出信号）的占空误差为 补偿。

公开(公告)号：US20140070969A1

公开(公告)日：2014-03-13

申请号：US14016246

申请日：2013-09-03

申请人： MEDIATEK INC.

发明人： Yun-Shiang Shu

IPC分类号： H03M3/00

CPC分类号： H03M3/322 ,  H03M3/388 ,  H03M3/458

摘要： A delta-sigma analog-to-digital converter (ΔΣ ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.

摘要翻译： Δ-Σ模数转换器（DeltaSigma ADC）具有Δ-Σ调制器，抽取滤波器和误差抑制电路。 Δ-Σ调制器接收模拟输入，并将模拟输入转换为第一数字输出。 抽取滤波器耦合到Δ-Σ调制器，并根据第一数字输出产生第二数字输出。 误差抑制电路耦合到抽取滤波器，并接收错误输入，并根据误差输入将错误输出注入第二数字输出。

公开(公告)号：US20130293401A1

公开(公告)日：2013-11-07

申请号：US13462345

申请日：2012-05-02

申请人： Paul M. Werking

发明人： Paul M. Werking

IPC分类号： H03M3/02 ,  H03M1/10

CPC分类号： H03M3/388 ,  H03M3/50

摘要： A sigma-delta digital-to-analog converter (SD DAC) exhibits undesirable distortion when implemented in an integrated circuit due to the non-linearity of polysilicon resistors used in the filtering stages of the SD DAC. By using resistors other than polysilicon for the output resistor of an SD DAC, distortion can be reduced or eliminated. Additionally or alternatively, by generating an error correction signal, the distortion can be corrected.

摘要翻译： 由于在SD DAC的滤波级中使用的多晶硅电阻的非线性，因此在集成电路中实现时，Σ-Δ数模转换器（SD DAC）表现出不期望的失真。 通过使用多晶硅之外的电阻作为SD DAC的输出电阻，可以减少或消除失真。 附加地或替代地，通过产生纠错信号，可以校正失真。

公开(公告)号：US20130176068A1

公开(公告)日：2013-07-11

申请号：US13719495

申请日：2012-12-19

申请人： Konosuke YAMAMOTO ,  Yoichi KIMURA

发明人： Konosuke YAMAMOTO ,  Yoichi KIMURA

IPC分类号： G06G7/04

CPC分类号： G06G7/04 ,  H03M3/388 ,  H03M3/458

摘要： A sensor output correction circuit includes an analog-to-digital converter configured to receive an input voltage corresponding to a sensor output of a sensor and a reference voltage that are selectively input to the analog-to-digital converter; and an arithmetic unit configured to correct output data, which is output from the analog-to-digital converter when the input voltage is input to the analog-to-digital converter, based on an output value that is output from the analog-to-digital converter when the reference voltage is input to the analog-to-digital converter. The arithmetic unit includes a multiply adder and a non-restoring divider.

摘要翻译： 传感器输出校正电路包括被配置为接收对应于传感器的传感器输出的输入电压和选择性地输入到模数转换器的参考电压的模拟 - 数字转换器; 以及算术单元，被配置为基于从所述模数转换器输出的输出值，校正从所述模数转换器输出的所述输出数据，所述输出数据在所述输入电压被输入到所述模数转换器时， 数字转换器，当参考电压输入到模数转换器时。 算术单元包括乘法加法器和非恢复分频器。

公开(公告)号：US07889109B2

公开(公告)日：2011-02-15

申请号：US12521441

申请日：2007-12-27

申请人： Yoshimitsu Murahashi

发明人： Yoshimitsu Murahashi

IPC分类号： H03M3/00

CPC分类号： H03F3/2173 ,  H03F2200/03 ,  H03F2200/331 ,  H03M3/388 ,  H03M3/50 ,  H03M7/3028 ,  H03M7/3033

摘要： A ΔΣ modulation digital-analogue converter of the present invention includes: a look-up table in which a correspondence relationship between each of a plurality of possible input values of an input signal externally supplied, and each of compensation values individually associated with the possible input values, are stored; and a nonlinear compensation circuit (6) for compensating the input signal externally supplied, based on a compensation value associated with the input signal among the compensation values, and supplying a ΔΣ modulation section (1) the input signal thus compensated. A sine wave is used as the input signal. The compensation value is set based on magnitudes of a spectrum of odd-order harmonics whose frequencies are A times more than a frequency of the sine wave (A is an odd number), the spectrum obtained in such a manner that an output of a D-Class amplifier (2) or an output of the ΔΣ modulation digital-analogue converter is subjected to a frequency analysis without a compensation with respect to the sine wave by the nonlinear compensation circuit (6). Therefore, it is possible to provide a ΔΣ modulation digital-analogue converter which (i) suppresses generation of odd-order harmonics with a simple circuit arrangement, and therefore (ii) is excellent in SNR and THD+N.

摘要翻译： A＆Dgr＆＆ 本发明的调制数模转换器包括：查找表，其中外部提供的输入信号的多个可能输入值中的每一个与分别与可能输入值相关联的每个补偿值之间的对应关系， 存储; 以及用于补偿外部输入信号的非线性补偿电路（6），其基于与所述补偿值中的输入信号相关联的补偿值，并且提供“ 调制部分（1）这样补偿的输入信号。 使用正弦波作为输入信号。 补偿值基于频率为正弦波的频率（A为奇数）的A倍的奇次谐波的频谱的大小设定，以使得D的输出 - 放大器（2）或输出＆Dgr＆ 通过非线性补偿电路（6）对调制数模转换器进行相对于正弦波的补偿的频率分析。 因此，可以提供一个＆Dgr＆ 调制数模转换器（i）以简单的电路布置抑制奇次谐波的产生，因此（ii）SNR和THD + N优异。