公开(公告)号：US07061416B2

公开(公告)日：2006-06-13

申请号：US11049955

申请日：2005-02-04

申请人： Toshiaki Nagai

发明人： Toshiaki Nagai

IPC分类号： H03M3/00

CPC分类号： H03M3/48 ,  H03M3/49

摘要： A sigma-delta A/D converter includes an A/D converter configured to output a digital signal, a signal-magnitude detecting circuit coupled to the output of the A/D converter to output a control signal responsive to a magnitude indicated by the digital signal, a D/A converter coupled to the output of the A/D converter and the output of the signal-magnitude detecting circuit to output an analog signal having a signal level responsive to the digital signal and the control signal, a differential circuit coupled to an external analog input and the output of the D/A converter to output a differential between the external analog input and the analog signal, and a filter circuit to couple between the output of the differential circuit and an input of the A/D converter, wherein the D/A converter is configured to control, in response to the control signal, a capacitance of a capacitor that discharges following charging of electric charge to supply an electric current of the analog signal.

摘要翻译： Σ-ΔA/ D转换器包括被配置为输出数字信号的A / D转换器，耦合到A / D转换器的输出端的信号幅度检测电路，以响应于由数字信号 信号，耦合到A / D转换器的输出的D / A转换器和信号幅度检测电路的输出，以输出响应于数字信号和控制信号的具有信号电平的模拟信号，差分电路耦合 外部模拟输入和D / A转换器的输出端输出外部模拟输入和模拟信号之间的差分，以及滤波电路，用于耦合差分电路的输出和A / D转换器的输入 ，其中所述D / A转换器被配置为响应于所述控制信号来控制放电后续充电电荷以提供所述模拟信号的电流的电容器的电容。

公开(公告)号：US06882861B2

公开(公告)日：2005-04-19

申请号：US09846841

申请日：2001-04-30

申请人： Carl M. Panasik ,  Roberto Sadkowski

发明人： Carl M. Panasik ,  Roberto Sadkowski

IPC分类号： H03M1/12 ,  H03M3/02 ,  H04M1/00

CPC分类号： H03M3/48

摘要： A wireless user terminal (42) and system (40) implementing a mixed signal CODEC (100) including an improved sigma-delta ADC (18) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. This sigma-delta analog-to-digital converter (18), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (20), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (20) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

摘要翻译： 公开了一种实现混合信号CODEC（100）的无线用户终端（42）和系统（40），该混合信号CODEC（100）包括将输入信号限制为开关电容器配置并避免在信号路径中增加电路开销的改进的Σ-ΔADC（18） 这里。 具有输入信号和输出信号的该Σ-Δ模数转换器（18）包括一个开关（SW＆lt; 1＆gt;），一个限幅电路（20）和一个已知的sigma- delta ADC（34）。 它通过在Σ-ΔADC的输入端限制信号来解决限幅信号问题（34）。 限幅电路（20）耦合到开关（SW＆lt; 1＆gt; 1）和Σ-ΔADC（34），用于切换施加到Σ-ΔADC的输入信号（v < 在）和至少一个阈值电压（V N n和V P p）中。

公开(公告)号：US06535153B1

公开(公告)日：2003-03-18

申请号：US09496756

申请日：2000-02-03

申请人： Clemens M. Zierhofer

发明人： Clemens M. Zierhofer

IPC分类号： H03M300

CPC分类号： H03M3/49 ,  H03M3/48

摘要： An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a +a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b +b], wherein b

摘要翻译： 自适应Σ-Δ调制器具有输入级，常规Σ-Δ调制器和适配级以及输出级。 输入级产生表示模拟输入信号和自适应信号之间的差的差信号，模拟输入信号的幅度处于第一范围[-a + a]。 常规的Σ-Δ调制器产生代表差分信号的中间数字输出序列，中间数字输出序列的幅度在第二范围[-b + b]，其中b

公开(公告)号：US06278392B1

公开(公告)日：2001-08-21

申请号：US09371114

申请日：1999-08-10

申请人： Eric Nestler

发明人： Eric Nestler

IPC分类号： H03M300

CPC分类号： H03M3/48 ,  G01R21/06

摘要： A system having an adjustable gain includes: a modulator, for producing a stream of digital words representative of an input analog signal; and, a gain adjustor, fed by a gain signal representative of the adjustable gain, for converting the stream of digital words produced by modulator into an output stream of bits representative of the gain adjusted input analog signal. The stream of stream of digital words produced by modulator, which represent the gain adjusted input analog signal, can be produced with an register for storing the gain signal and an adder. Further, the stream of digital words bits produced by modulator can fed to an compact sinc filter for conversion into digital words which represent digital samples on the gain adjusted input analog signal. The system includes a sigma-delta modulator for producing a stream of digital words having values, M or N, such stream of digital words bits being representative of an input analog signal, X(t) fed to the modulator. A gain adjustor is fed by the sigma-delta modulator and a gain signal representative of the variable gain. The gain adjustor converts the stream of digital words produced by sigma delta modulator into an output stream of digital words having values P or Q, where P=M−(G−1)/2 and Q=N+(G−1)/2, such output stream of digital words representing an output analog signal Z(t)=GX(t).

摘要翻译： 具有可调增益的系统包括：调制器，用于产生表示输入模拟信号的数字字流; 以及增益调节器，其由表示可调增益的增益信号馈送，用于将由调制器产生的数字字流转换为表示增益调整的输入模拟信号的位的输出流。 可以通过用于存储增益信号的寄存器和加法器产生由调制器产生的代表增益调整的输入模拟信号的数字字的流。 此外，由调制器产生的数字字比特流可以馈送到紧凑的sinc滤波器，以转换成表示增益调整的输入模拟信号上的数字样本的数字字。 该系统包括用于产生具有值M或N的数字字流的Σ-Δ调制器，这种数字字比特流表示输入到调制器的输入模拟信号X（t）。 增益调节器由Σ-Δ调制器和表示可变增益的增益信号馈送。 增益调节器将由Σ-Δ调制器产生的数字字流转换成具有值P或Q的数字字的输出流，其中P = M-（G-1）/ 2和Q = N +（G-1）/ 2 表示输出模拟信号Z（t）= GX（t）的数字字的输出流。

公开(公告)号：US08964860B2

公开(公告)日：2015-02-24

申请号：US14115566

申请日：2012-03-13

申请人： Shinichi Hori

发明人： Shinichi Hori

IPC分类号： H04B14/06 ,  H04L27/12 ,  H03M3/00

CPC分类号： H04L27/12 ,  H03F3/217 ,  H03F3/24 ,  H03M3/48 ,  H03M3/50

摘要： To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.

摘要翻译： 提供一种数字调制器，包括：信号调节器（105），其设有多条输出线，并且输出到与输入信号的电平所属的范围相对应的输出线的信号 对应于输入信号电平的电平; 多个内部数字调制器（111-1至111-N），每个内部数字调制器（111-1至111-N）被提供以对应于多个输出线中的每一个，并且对相应输出线的信号执行Δ-Σ调制以输出 调制信号; 以及对由多个内部数字调制器分别输出的多个调制信号进行编码的编码器（113）。

公开(公告)号：US20120328129A1

公开(公告)日：2012-12-27

申请号：US13580153

申请日：2011-03-16

申请人： Han M. Schuurmans

发明人： Han M. Schuurmans

IPC分类号： H04R3/00

CPC分类号： H03M1/183 ,  H03M3/48 ,  H04R3/02 ,  H04R2410/00

摘要： A microphone circuit has a clip detection circuit (30) which detects when an analogue to digital converter (ADC, 12) output has reached a threshold. A variable capacitance (34a, 34b, 34c, 34d), which functions as a variable input load associated with the microphone (11), is controlled based on the clip detection circuit output, the feedback is thus based on the ADC out-put level, and the processing of this signal can be implemented without requiring baseband processing of the signal—it can simply be based on a state of the ADC output.

摘要翻译： 麦克风电路具有检测模拟数字转换器（ADC，12）输出何时达到阈值的片段检测电路（30）。 用作与麦克风（11）相关联的可变输入负载的可变电容（34a，34b，34c，34d）基于片段检测电路输出来控制，因此反馈基于ADC输出电平 ，并且可以在不需要对信号进行基带处理的情况下实现该信号的处理 - 其可以简单地基于ADC输出的状态。

公开(公告)号：US20100164773A1

公开(公告)日：2010-07-01

申请号：US12293744

申请日：2006-03-23

申请人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

发明人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

IPC分类号： H03M3/00

CPC分类号： H03M3/48 ,  H03M1/181 ,  H03M1/20 ,  H03M3/49

摘要： An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

摘要翻译： 集成电路包括并入具有正向通路中的模数转换器和反馈路径中的数模转换器的Δ-Σ调制环的Δ-Σ调制器，使得ADC被布置为接收 模拟输入信号。 ADC可操作地耦合到自动测距逻辑，其布置成从表示模拟输入信号的ADC移位数字输出信号，以抵消模拟输入信号的输入变化的影响。 以这种方式，具有自恢复技术的自动量程逻辑的应用支持减少多位Δ-ΣADC中所需的比较器的数量。

公开(公告)号：US06795002B2

公开(公告)日：2004-09-21

申请号：US10326706

申请日：2002-12-23

申请人： Sandeep K. Gupta

发明人： Sandeep K. Gupta

IPC分类号： H03M300

CPC分类号： H03M3/48 ,  H03M3/414

摘要： An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2n subranges. A first subrange of the 2n subranges is bounded by a lowest value of the range, a second subrange of the 2n subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2n subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2n−1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2n−1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable. A second gain of a stability correction gain element of a coupling stage connected to the downstream modulator is set so that a swing of the analog signal remains within a dynamic range of the downstream modulator stage.

摘要翻译： 下行调制级的n位量化器被配置为从具有范围的模拟信号产生n位量化信号。 n位量化器将范围分为2 个子范围。 2 子范围的第一个子范围由范围的最小值限定，2 子范围的第二子范围由范围的最大值界定，并且至少一个剩余子范围为2 < n>子范围位于第一和第二子范围之间。 第一和第二子范围大于总范围的{1 / [2（2 -1）]}。 每个至少一个剩余的子范围测量值小于总范围的[1 /（2 -1）]。 设置下游调制器级的积分器的第一增益，使得下游调制器级稳定。 设置连接到下游调制器的耦合级的稳定性校正增益元件的第二增益，使得模拟信号的摆幅保持在下游调制器级的动态范围内。

公开(公告)号：US20030146865A1

公开(公告)日：2003-08-07

申请号：US10357613

申请日：2003-02-04

发明人： Clemens M. Zierhofer

IPC分类号： H03M003/00

CPC分类号： H03M3/49 ,  H03M3/48

摘要： An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range nullnulla nullanull. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range nullnullb nullbnull, wherein b

公开(公告)号：US20020160732A1

公开(公告)日：2002-10-31

申请号：US09846841

申请日：2001-04-30

发明人： Carl M. Panasik ,  Roberto Sadkowski

IPC分类号： H04B001/06

CPC分类号： H03M3/48

摘要： A wireless user terminal (42) and system (40) implementing a mixed signal CODEC (100) including an improved sigma-delta ADC (18) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. This sigma-delta analog-to-digital converter (18), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (20), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (20) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

摘要翻译： 公开了一种实现混合信号CODEC（100）的无线用户终端（42）和系统（40），该混合信号CODEC（100）包括将输入信号限制为开关电容器配置并避免在信号路径中增加电路开销的改进的Σ-ΔADC（18） 这里。 具有输入信号和输出信号的Σ-Δ模数转换器（18）包括开关（sw1），限幅电路（20）和已知的Σ-ΔADC（34）。 它通过在Σ-ΔADC的输入端限制信号来解决限幅信号问题（34）。 限幅电路（20）耦合到开关（sw1）和Σ-ΔADC（34），用于切换在输入信号（vin）和至少一个阈值电压（Vn和Vp）之间施加到Σ-ΔADC的电压 ）。