公开(公告)号：US07969339B2

公开(公告)日：2011-06-28

申请号：US12293744

申请日：2006-03-23

申请人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

发明人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

IPC分类号： H03M3/00

CPC分类号： H03M3/48 ,  H03M1/181 ,  H03M1/20 ,  H03M3/49

摘要： An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

摘要翻译： 集成电路包括并入具有正向通路中的模数转换器和反馈路径中的数模转换器的Δ-Σ调制环路的Δ-Σ调制器，使得ADC被布置为接收 模拟输入信号。 ADC可操作地耦合到自动测距逻辑，其布置成从表示模拟输入信号的ADC移位数字输出信号，以抵消模拟输入信号的输入变化的影响。 以这种方式，具有自恢复技术的自动量程逻辑的应用支持减少多位Δ-ΣADC中所需的比较器的数量。

公开(公告)号：US20100164773A1

公开(公告)日：2010-07-01

申请号：US12293744

申请日：2006-03-23

申请人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

发明人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

IPC分类号： H03M3/00

CPC分类号： H03M3/48 ,  H03M1/181 ,  H03M1/20 ,  H03M3/49

摘要： An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

摘要翻译： 集成电路包括并入具有正向通路中的模数转换器和反馈路径中的数模转换器的Δ-Σ调制环的Δ-Σ调制器，使得ADC被布置为接收 模拟输入信号。 ADC可操作地耦合到自动测距逻辑，其布置成从表示模拟输入信号的ADC移位数字输出信号，以抵消模拟输入信号的输入变化的影响。 以这种方式，具有自恢复技术的自动量程逻辑的应用支持减少多位Δ-ΣADC中所需的比较器的数量。

公开(公告)号：US20120180924A1

公开(公告)日：2012-07-19

申请号：US13392812

申请日：2010-09-03

申请人： Stéphane Auvray ,  Eric Carpentier ,  Patrick Clement

发明人： Stéphane Auvray ,  Eric Carpentier ,  Patrick Clement

IPC分类号： B60C17/04 ,  B23P11/02

CPC分类号： B60C17/06 ,  B60C2017/068 ,  Y10T29/49492

摘要： The present invention relates to a flat-running device intended for being fitted on an assembly mounted on a tubeless one-piece rim for an automobile, said mounted assembly including said device, and to a method for mounting and/or removing said mounted assembly. The device according to the invention (1) includes a ring (2) with a radially internal mounting surface for the device, intended to closely match the hollow section of the rim (11), the ring having an open structure with two ends held closely facing one another by a means (5) for clamping the ring. According to the invention, at least one transverse notch (6), the two edges and the bottom of which are located under one of the ends of the ring, is formed in at least one of said side portions (3a), forming a circumferential lip which projects axially from the corresponding side wall of the ring, which includes said recess and is suitable for wedging the ring in the hollow section of the rim, such as to enable, via said notch, transverse insertion of a tool (7) such as a lever between the rim and said mounting surface in order to facilitate the operations of mounting and/or removing the device on the rim.

摘要翻译： 本发明涉及一种用于安装在安装在用于汽车的无内胎一体式轮辋上的组件上的平行装置，所述安装组件包括所述装置，以及用于安装和/或移除所述安装组件的方法。 根据本发明的装置（1）包括具有用于装置的径向内部安装表面的环（2），用于紧密地匹配轮辋（11）的中空部分，所述环具有开口结构，其两端紧密地保持 通过用于夹紧环的装置（5）彼此面对。 根据本发明，至少一个横向切口（6），其两个边缘和底部位于环的一个端部下方，形成在至少一个所述侧部（3a）中，形成周向 所述唇部从所述环的相应侧壁轴向突出，所述唇部包括所述凹部并且适于将所述环楔入所述边缘的中空部分，以便经由所述切口能够横向插入工具（7） 作为在边缘和所述安装表面之间的杠杆，以便于在边缘上安装和/或移除装置的操作。

公开(公告)号：US07953382B1

公开(公告)日：2011-05-31

申请号：US11970443

申请日：2008-01-07

申请人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

发明人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

IPC分类号： H04B7/08

CPC分类号： H04B1/034

摘要： Methods and apparatuses for quiet spot detection for radio frequency transmission thereon. According to various embodiments, a device may include a local receiver configured to evaluate one or more frequencies of a frequency band to determine a quiet spot frequency, the device further including a local transmitter configured to transmit signals at the quiet spot frequency.

摘要翻译： 用于无线电频率传输的安静点检测的方法和装置。 根据各种实施例，设备可以包括被配置为评估频带的一个或多个频率以确定安静点频率的本地接收机，该设备还包括被配置为以安静点频率发射信号的本地发射机。

公开(公告)号：US20060145900A1

公开(公告)日：2006-07-06

申请号：US10515561

申请日：2003-05-19

申请人： Patrick Clement ,  Nadim Khlat

发明人： Patrick Clement ,  Nadim Khlat

IPC分类号： H03M3/00

CPC分类号： H03M3/466 ,  H03M3/41

摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).

摘要翻译： 一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法 第一或第二平移Σ-Δ模数转换器（21,22）的转换。 并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。 通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

公开(公告)号：US06856266B2

公开(公告)日：2005-02-15

申请号：US10490875

申请日：2002-09-09

申请人： Patrick Clement ,  Nadim Khlat ,  Daniel B Schwartz

发明人： Patrick Clement ,  Nadim Khlat ,  Daniel B Schwartz

IPC分类号： H03M3/02 ,  H03M3/00 ,  H03M1/00 ,  H03M7/00

CPC分类号： H03M3/496

摘要： A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with the existing software.

摘要翻译： 多速率模数转换器（19）耦合到作为参考时钟的单晶振荡器（17），并且具有至少两个单独的通道，其布置成以两个不同的时钟速率对输入数据进行采样和转换。 每个通道从参考时钟导出时钟信号。 与每个通道相关联的是包括调制器（12），滤波器（14）和重采样器（18）的Σ-Δ转换器（10a，10b）。 调制器（12）接收输入数据并向滤波器（14）提供数据信号，滤波器本身将经过滤波的数据信号提供给相关联的数据重采样器。 数据重采样器重新采样数据并提供数字输出信号。 由于在数字领域中采用了与信号处理，速度和低噪声注入相关的优点。 类似地，当调制器（12）的输出是数字形式时，它可以容易地和现有的软件被操纵和处理。

公开(公告)号：US08428535B1

公开(公告)日：2013-04-23

申请号：US12175034

申请日：2008-07-17

申请人： David Cousinard ,  Patrick Clement ,  Cao-Thong Tu

发明人： David Cousinard ,  Patrick Clement ,  Cao-Thong Tu

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H03G3/20 ,  A42B3/225 ,  A42B3/24

摘要： A controller in a receiver monitors RSSI and AGC gain levels to determine signal conditions and adjust filter performance accordingly to optimize power consumption while providing acceptable signal quality. When RSSI level is high and AGC gain is low, a strong signal-of-interest is present. In this case, adaptive filter bias currents may be reduced raise the noise floor and degrade intermodulation to reduce power consumption because the strong signal-of-interest can tolerate the higher noise and distortion. When the RSSI level is low and AGC gain is high, a weak signal is present a low noise mode may be effected by increasing bias current to filters used to lower the noise floor, but intermodulation effects may still be tolerated so those filters may be cut back. Other cases are supported. RSSI and AGC gain level thresholds may be dynamically altered based on relative RSSI and AGC levels.

摘要翻译： 接收机中的控制器监视RSSI和AGC增益电平，以确定信号状况并相应地调整滤波器性能，以优化功耗，同时提供可接受的信号质量。 当RSSI电平高且AGC增益低时，存在强烈的感兴趣的信号。 在这种情况下，自适应滤波器偏置电流可能会降低，从而降低本底噪声并降低互调，从而降低功耗，因为强信号可以容忍更高的噪声和失真。 当RSSI电平低并且AGC增益高时，存在弱信号，低噪声模式可以通过增加用于降低本底噪声的滤波器的偏置电流来实现，但互调效应仍然可以被允许，因此可以切割这些滤波器 背部。 其他案例得到支持。 可以基于相对RSSI和AGC电平动态地改变RSSI和AGC增益电平门限。

公开(公告)号：US08320860B1

公开(公告)日：2012-11-27

申请号：US13117460

申请日：2011-05-27

申请人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

发明人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

IPC分类号： H04B7/08

CPC分类号： H04B1/034

摘要： Methods and apparatuses for quiet spot detection for radio frequency transmission thereon. According to various embodiments, a device may include a local receiver configured to evaluate one or more frequencies of a frequency band to determine a quiet spot frequency, the device further including a local transmitter configured to transmit signals at the quiet spot frequency.

摘要翻译： 用于无线电频率传输的安静点检测的方法和装置。 根据各种实施例，设备可以包括被配置为评估频带的一个或多个频率以确定安静点频率的本地接收机，该设备还包括被配置为以安静点频率发射信号的本地发射机。

公开(公告)号：US08116706B1

公开(公告)日：2012-02-14

申请号：US11970133

申请日：2008-01-07

申请人： Patrick Clement ,  King Chu Tsai ,  Heinz Maeder

发明人： Patrick Clement ,  King Chu Tsai ,  Heinz Maeder

IPC分类号： H04B1/18

CPC分类号： H04B1/1638 ,  H04B1/1027

摘要： To calibrate a bandpass filter, a received signal strength corresponding to a received communication channel is determined. A variable element of the bandpass filter is adjusted based on the received signal strength of the received communication channel to calibrate the bandpass filter.

摘要翻译： 为了校准带通滤波器，确定与接收到的通信信道相对应的接收信号强度。 基于所接收的通信信道的接收信号强度来调整带通滤波器的可变元件以校准带通滤波器。

公开(公告)号：US08014477B1

公开(公告)日：2011-09-06

申请号：US11592357

申请日：2006-11-02

申请人： King Chun Tsai ,  Patrick Clement ,  David Cousinard

发明人： King Chun Tsai ,  Patrick Clement ,  David Cousinard

IPC分类号： H03D1/04

CPC分类号： H03M3/458 ,  H01L51/524 ,  H03M1/004 ,  H03M1/12

摘要： A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

摘要翻译： 提出了包括调谐器电路和转换器电路的接收器。 调谐器电路提供对应于在所选频道上接收的调制信号的模拟信号。 转换器电路包括采样时钟，该采样时钟用于以与采样时钟的频率对应的转换速率将模拟信号转换为数字信号。 采样时钟可在至少两个不同的时钟频率之间选择。