公开(公告)号：US11750184B1

公开(公告)日：2023-09-05

申请号：US17876503

申请日：2022-07-28

申请人： Montage Electronics (Shanghai) Co., Ltd.

发明人： Li Quan ,  Xuexin Ding ,  Liang Zhang ,  Zhongyuan Chang ,  Yufei Gu ,  Lixin Jiang ,  Gang Yan ,  Zongjie Hu

IPC分类号： H03K5/00 ,  H03K5/1534 ,  H03K5/1252 ,  H03K5/01

CPC分类号： H03K5/1534 ,  H03K5/1252 ,  H03K5/01

摘要： The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.

公开(公告)号：US11742841B2

公开(公告)日：2023-08-29

申请号：US17898111

申请日：2022-08-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Vibha Goenka

IPC分类号： H03K5/1252 ,  H03K3/017 ,  H03K19/20 ,  H03K5/24 ,  H03K3/037 ,  H03K19/003

CPC分类号： H03K5/1252 ,  H03K3/017 ,  H03K3/037 ,  H03K5/24 ,  H03K19/00346 ,  H03K19/20

摘要： A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

公开(公告)号：US11728797B2

公开(公告)日：2023-08-15

申请号：US17660916

申请日：2022-04-27

申请人： International Business Machines Corporation

发明人： David C. Mckay ,  Abhinav Kandala ,  Srikanth Srinivasan

IPC分类号： H03K17/92 ,  H03K5/1252

CPC分类号： H03K5/1252 ,  H03K17/92

摘要： Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel. In various instances, the first resonator can have a first resonant frequency less than the first operational frequency and the second operational frequency, and the second resonator can have a second resonant frequency greater than the first operational frequency and the second operational frequency. In various other embodiments, the multi-resonant architecture can comprise a resonator, a first end of which can be capacitively coupled to the first qubit and to the second qubit, and a second end of which can be coupled to ground. In various instances, the resonator can have a first harmonic less than the first operational frequency and the second operational frequency, and can have a second harmonic greater than the first operational frequency and the second operational frequency. In various other embodiments, the multi-resonant architecture can comprise a resonator and a direct coupler. In various embodiments, the resonator and the direct coupler can both capacitively couple the first qubit to the second qubit, and the resonator and the direct coupler can be in parallel. In various cases, the direct coupler can couple opposite pads of the first qubit and the second qubit. In various embodiments, a first end of the resonator can be capacitively coupled to the first qubit and the second qubit, a second end of the resonator can be coupled to ground, and the direct coupler can capacitively couple common pads of the first qubit and the second qubit.

公开(公告)号：US11671289B2

公开(公告)日：2023-06-06

申请号：US17474800

申请日：2021-09-14

申请人： NXP USA, Inc.

发明人： Ranjeet Kumar Gupta ,  Siamak Delshadpour ,  Kenneth Jaramillo

IPC分类号： H04L25/06 ,  G01R23/15 ,  H04B1/12 ,  H04L25/08 ,  H03K5/13 ,  H03K5/1252

CPC分类号： H04L25/069 ,  G01R23/15 ,  H03K5/13 ,  H04B1/12 ,  H04L25/085 ,  H03K5/1252

摘要： Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

公开(公告)号：US20230155582A1

公开(公告)日：2023-05-18

申请号：US17716101

申请日：2022-04-08

申请人： NUVOTON TECHNOLOGY CORPORATION

发明人： YUNG-CHI LAN

IPC分类号： H03K5/1252 ,  H03K21/08 ,  H03K3/037 ,  G06F1/06

CPC分类号： H03K5/1252 ,  H03K21/08 ,  H03K3/037 ,  G06F1/06

摘要： A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

公开(公告)号：US11581883B2

公开(公告)日：2023-02-14

申请号：US17691804

申请日：2022-03-10

申请人： Hirose Electric Co., Ltd.

发明人： Ching-Chao Huang ,  Jeremy Buan ,  Jingqian Tian ,  Tadashi Ohshida

IPC分类号： H03K5/12 ,  H03K5/1252 ,  H03K5/00

摘要： A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

公开(公告)号：US20220376684A1

公开(公告)日：2022-11-24

申请号：US17794992

申请日：2020-03-24

申请人： Mitsubishi Electric Corporation

发明人： Shinobu NAGASAWA

IPC分类号： H03K5/1252

摘要： A compensation signal generator generates a compensation signal for canceling an electromagnetic noise on a connection line on the basis of a detection signal of a noise detector. A compensation signal injector injects the compensation signal into the connection line. A compensation signal detector outputs a detection signal of the compensation signal. A low-frequency component subtraction unit amplifies a component in a predetermined first frequency region of the detection signal and negatively feeds back the amplified component to the compensation signal generator. An intermediate frequency component addition unit positively feeds back a component of a predetermined second frequency that is higher than the first frequency region in the detection signal to the compensation signal generator.

公开(公告)号：US20220352881A1

公开(公告)日：2022-11-03

申请号：US17662290

申请日：2022-05-06

申请人： Alpha and Omega Semiconductor International LP

发明人： Richard Schmitz ,  Tsing Hsu

IPC分类号： H03K5/1252 ,  H04B15/00

摘要： Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.

公开(公告)号：US20220329239A1

公开(公告)日：2022-10-13

申请号：US17634590

申请日：2019-08-13

申请人： Nanowave Technologies Inc.

发明人： Charles William Tremlett NICHOLLS

IPC分类号： H03K5/1252 ,  H03K5/14 ,  H03D7/00

摘要： A transposed delay line oscillator including a mode selection filter and a transposed delay line is provided. An output of the transposed delay line is coupled to an input of the mode selection filter to establish an oscillator loop. Based on the transposed delay line output, the mode selection filter generates a mode selection signal including an isolated oscillatory mode, in a Radio Frequency (RF) band. The transposed delay line receives the mode selection signal for transposition to an intermediate frequency of an intermediate frequency (IF) delay line. The IF delay line includes a delay filter and a phase noise suppression loop configured to suppress de-correlated transposition phase noise resulting from a delay of the delay filter. Suppression of phase noise in the IF delay line enables cancellation of transposition phase noise when transposing the IF delay line output to the RF band.

公开(公告)号：US20220311431A1

公开(公告)日：2022-09-29

申请号：US17616692

申请日：2019-08-27

申请人： Mitsubishi Electric Corporation

发明人： Junichi NAKASHIMA

IPC分类号： H03K17/16 ,  H02M7/537 ,  H03K5/1252 ,  H01L25/16 ,  H01L25/18 ,  H01L23/538

摘要： A power semiconductor module includes a semiconductor switching element, a gate control pattern to which a gate electrode of the semiconductor switching element is connected, a source control pattern to which a source electrode of the semiconductor switching element is connected, a capacitor to form a low-pass filter, a capacitor arrangement pattern to which one end of the capacitor is connected, and a wire. The other end of the capacitor is connected to the source control pattern. The wire electrically connects the capacitor arrangement pattern and the gate control pattern.