公开(公告)号：US20110279872A1

公开(公告)日：2011-11-17

申请号：US13124708

申请日：2009-10-19

Applicant: Haifeng Li ,  Shixiong Ma ,  Bin Yang ,  Lidong Wang

Inventor： Haifeng Li ,  Shixiong Ma ,  Bin Yang ,  Lidong Wang

IPC: H04N1/405

CPC classification number: H04N1/52

Abstract: An image processing method includes: generating a stochastic screening dither matrix (S101); performing a centered positive-negative conversion operation on the stochastic screening dither matrix (S102); generating a screen dot dither contrast matrix for each color surface according to the stochastic screening dither matrix after being subjected to the positive-negative conversion operation and a stochastic screening dither threshold set for each color surface of an image; performing a logical “and” operation between each data item in a one-bit amplitude modulation screen dot matrix of each color surface of the image and a data item at a corresponding position in the screen dot dither contrast matrix of the color surface, and using a result as a processed value of a corresponding data item in the one-bit amplitude modulation screen dot matrix of the color surface. An apparatus corresponding to the image processing method is also provided. According to the above-described image processing method and apparatus, the problem in the prior art of an excess of pure-color pixels existing in an original one-bit dot matrix can be resolved.

Abstract translation: 一种图像处理方法包括：产生随机筛选抖动矩阵（S101）; 对随机筛选抖动矩阵执行中心正负转换操作（S102）; 根据随机筛选抖动矩阵在进行正负转换操作之后产生每个颜色表面的屏幕点抖动对比度矩阵，以及为图像的每个颜色表面设置的随机屏蔽抖动阈值; 在图像的每个颜色表面的一位幅度调制屏幕点阵中的每个数据项之间执行逻辑“和”操作，以及在颜色表面的屏幕点抖动对比矩阵中的相应位置处的数据项，并且使用 作为颜色表面的一位幅度调制屏幕点阵中的相应数据项的处理值的结果。 还提供了与图像处理方法对应的装置。 根据上述图像处理方法和装置，可以解决现有技术中存在于原始一位点阵中的纯色像素的过剩问题。

公开(公告)号：US20110254092A1

公开(公告)日：2011-10-20

申请号：US12759969

申请日：2010-04-14

Applicant: Bin Yang ,  Michael Hargrove

Inventor： Bin Yang ,  Michael Hargrove

IPC: H01L27/092 ,  H01L21/31

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/12 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow.

Abstract translation: 在ETSOI层，ETSOI衬底的薄Si层上形成半导体，具有增强的沟道应力。 实施例包括在ETSOI层的背面上具有双重应力衬垫的半导体器件。 一个实施例包括在背面基板上形成包括超薄Si层的ETSOI衬底，其上具有诸如BOX之间的绝缘层（例如BOX），在Si表面上形成半导体器件，通过CMP和 绝缘层，如通过湿蚀刻，并且在与半导体器件相对的剩余Si层的背面上形成应力衬垫。 在ETSOI层的背面使用应力衬垫增强了通道应力，而不改变ETSOI半导体工艺流程。

公开(公告)号：US20110246138A1

公开(公告)日：2011-10-06

申请号：US12912732

申请日：2010-10-26

Applicant: Yi-Jen Chung ,  Chi-Pei Huang ,  Ching-Ning Chiu ,  Jin-Bin Yang

Inventor： Yi-Jen Chung ,  Chi-Pei Huang ,  Ching-Ning Chiu ,  Jin-Bin Yang

IPC: G06F11/30 ,  G06F15/00

CPC classification number: G06F13/4072

Abstract: A hardware status detecting circuit for detecting a hardware status of a target apparatus includes a plurality of hardware status detectors operating in response to the hardware status of the target apparatus, and a signal processing unit coupled to the hardware status detectors for generating a hardware status detecting signal having information of operational statuses of the hardware status detectors embedded therein.

Abstract translation: 用于检测目标设备的硬件状态的硬件状态检测电路包括响应于目标设备的硬件状态操作的多个硬件状态检测器，以及耦合到硬件状态检测器的信号处理单元，用于产生硬件状态检测 信号，其具有嵌入其中的硬件状态检测器的操作状态信息。

公开(公告)号：US08023152B2

公开(公告)日：2011-09-20

申请号：US11912846

申请日：2005-11-02

Applicant: Haifeng Li ,  Bin Yang ,  Shixiong Ma

Inventor： Haifeng Li ,  Bin Yang ,  Shixiong Ma

IPC: H04N1/405

CPC classification number: H04N1/4052 ,  H04N1/4055

Abstract: The present invention relates to a method for producing halftone dots in the field of image hard copying, more particularly to a method for frequency-modulation screening using error diffusion based on dual-feedback. In the known frequency-modulation and amplitude-modulation screening technology, it is hard to output a halftone image with high quality using an output equipment with a low resolution (600 dpi) and the satisfactory effect of representing the gradations of the original image in detail and holding the smoothness of the original image can not be achieved. By using the dual-feedback technology based on a basic algorithm of the error distribution, the method in the present invention realizes the organic combination of the conventional frequency-modulation and amplitude-modulation screens and achieves the effect of mixed screening. The method in the present invention can effectively solve the problem of losing gradations of dots in an output equipment with low resolution and can reduce the moire caused by the random distribution characteristic so as to output halftone images with high quality and full gradations.

Abstract translation: 本发明涉及一种在图像硬拷贝领域制造半色调点的方法，更具体地说，涉及一种使用基于双重反馈的误差扩散进行频率调制筛选的方法。 在已知的调频和幅度调制技术中，使用低分辨率（600dpi）的输出设备输出具有高品质的半色调图像是困难的，并且具有令人满意的效果，其表示原始图像的灰度 并保持原始图像的平滑度无法实现。 通过使用基于误差分布的基本算法的双反馈技术，本发明的方法实现了常规频率调制和幅度调制屏幕的有机组合，并实现了混合筛选的效果。 本发明的方法可以有效地解决在分辨率低的输出设备中丢失点的灰度的问题，并且可以减少由随机分布特性引起的波纹，从而输出具有高质量和全等级的半色调图像。

公开(公告)号：US20110215687A1

公开(公告)日：2011-09-08

申请号：US12894253

申请日：2010-09-30

Applicant: YUN-LUNG CHEN ,  ZHAO-BIN YANG ,  WEI-YONG MA

Inventor： YUN-LUNG CHEN ,  ZHAO-BIN YANG ,  WEI-YONG MA

IPC: H05K5/02

CPC classification number: H05K5/02

Abstract: An apparatus includes a case and a bezel. The case includes a wall. A wall flange is located on the wall. A plurality of pairs of cutouts is defined in an edge of the wall flange, and an extending tab is located between each pair of cutouts. A plurality of locking members is located on the bezel, the locking members engaged in the receiving openings.

Abstract translation: 一种装置包括壳体和挡板。 案件包括一堵墙。 墙壁法兰位于墙上。 多个成对的切口限定在壁凸缘的边缘中，并且延伸突片位于每对切口之间。 多个锁定构件位于挡板上，锁定构件接合在接收开口中。

公开(公告)号：US20110169083A1

公开(公告)日：2011-07-14

申请号：US12687607

申请日：2010-01-14

Applicant: Bin YANG ,  Rohit PAL ,  Michael HARGROVE

Inventor： Bin YANG ,  Rohit PAL ,  Michael HARGROVE

IPC: H01L29/786 ,  H01L21/86

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20110147809A1

公开(公告)日：2011-06-23

申请号：US12644092

申请日：2009-12-22

Applicant: Bin Yang ,  Devendra Sadana ,  Christian Lavoie ,  Ahmet Ozcan

Inventor： Bin Yang ,  Devendra Sadana ,  Christian Lavoie ,  Ahmet Ozcan

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method includes forming a silicon germanium layer, forming a layer comprising carbon and silicon on a top surface of the silicon germanium layer, forming a metal layer above the layer comprising carbon and silicon, and performing a thermal treatment to convert at least the layer comprising carbon and silicon to form a metal silicide layer.

Abstract translation: 一种方法包括形成硅锗层，在硅锗层的顶表面上形成包含碳和硅的层，在包含碳和硅的层之上形成金属层，并进行热处理以至少将含有 碳和硅以形成金属硅化物层。

公开(公告)号：US20110141723A1

公开(公告)日：2011-06-16

申请号：US12690251

申请日：2010-01-20

Applicant: CHIH-MING LAI ,  HONG-BIN YANG ,  MING-YOUNG SHIAO

Inventor： CHIH-MING LAI ,  HONG-BIN YANG ,  MING-YOUNG SHIAO

IPC: F21V29/00 ,  F21S4/00

CPC classification number: F21V19/0045 ,  F21K9/272 ,  F21Y2103/10 ,  F21Y2107/30 ,  F21Y2107/90 ,  F21Y2115/10

Abstract: An LED lamp includes an envelope, two covers, a mounting board and a plurality of LEDs. The covers engages with opposite ends of the envelope. Each of the covers has an electrically conductive part. The mounting board is received in the envelope. Two ends of the mounting board electrically connect with the electrically conductive parts of the two covers, respectively. The LEDs are disposed on the mounting board and received in the envelope.

Abstract translation: LED灯包括外壳，两个盖，安装板和多个LED。 盖子与信封的两端接合。 每个盖具有导电部分。 安装板接收在信封中。 安装板的两端分别与两个盖的导电部分电连接。 LED设置在安装板上并接收在信封中。

公开(公告)号：US07960229B2

公开(公告)日：2011-06-14

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Scott Luning

Inventor： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US07930559B1

公开(公告)日：2011-04-19

申请号：US11480346

申请日：2006-06-30

Applicant: Arthur Beaverson ,  Bin Yang ,  Jamie Pocas

Inventor： Arthur Beaverson ,  Bin Yang ,  Jamie Pocas

IPC: G06F11/28

CPC classification number: G06F17/30368 ,  G06F11/1448 ,  G06F11/1453 ,  G06F11/1456 ,  G06F11/1458 ,  G06F11/1461

Abstract: Described are techniques for storing data. A plurality of data portions and a corresponding token for each of the data portions are received. Each of said plurality of data portions is to be stored by one of a plurality of processes and each token has a corresponding token value. Each of the data portions is stored at a storage location on a device allocated for use by one of said plurality of processes. An entry is written in a log file in accordance with said storing of the data portion. The log file is a private log file of one of the plurality processes. An access structure used to access stored data portions is updated. The access structure is indexed by token values of the stored data portions. The updating of the access structure is performed in accordance with log entries from private log files of the plurality of processes.

Abstract translation: 描述了用于存储数据的技术。 接收用于每个数据部分的多个数据部分和相应的令牌。 所述多个数据部分中的每一个将通过多个进程中的一个进行存储，并且每个令牌具有对应的令牌值。 每个数据部分被存储在被分配供所述多个进程之一使用的设备上的存储位置处。 根据所述数据部分的存储，将条目写入日志文件。 日志文件是多个进程之一的专用日志文件。 用于访问存储的数据部分的访问结构被更新。 访问结构由存储的数据部分的令牌值索引。 根据多个进程的专用日志文件的日志条目执行访问结构的更新。