公开(公告)号：US20220399372A1

公开(公告)日：2022-12-15

申请号：US17344391

申请日：2021-06-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Uzma RANA ,  Siva P. ADUSUMILLI ,  Steven M. SHANK

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US11513286B2

公开(公告)日：2022-11-29

申请号：US17026799

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/12

Abstract: Structures for an optical power splitter/combiner and methods of forming a structure for an optical power splitter/combiner. A first waveguide core is positioned adjacent to a second waveguide core. The first waveguide core includes a first end surface and a first tapered section that tapers toward the first end surface. The second waveguide core includes a second end surface and a second tapered section that tapers toward the second end surface. A third waveguide core is positioned in a different level than the first waveguide core and the second waveguide core. The third waveguide core includes a third end surface and a third tapered section that tapers toward the third end surface. The third tapered section includes a portion laterally positioned between the first tapered section of the first waveguide core and the second tapered section of the second waveguide core.

公开(公告)号：US20220352210A1

公开(公告)日：2022-11-03

申请号：US17306078

申请日：2021-05-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. LEVY ,  Siva P. ADUSUMILLI ,  Alvin J. JOSEPH ,  Ramsey HAZBUN

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

公开(公告)号：US11488967B2

公开(公告)日：2022-11-01

申请号：US17211903

申请日：2021-03-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jörg D. Schmid ,  Nigel Chan

IPC: G11C11/417 ,  H01L27/11 ,  G11C11/412

Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure. Various interconnects (including, but not limited to, silicide bridges and/or contact straps) provide the internal and electrical connections required for making the 8T SRAM cell operational and for incorporating the 8T SRAM cell into an array of such cells.

公开(公告)号：US11482456B2

公开(公告)日：2022-10-25

申请号：US16360183

申请日：2019-03-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

公开(公告)号：US11476289B2

公开(公告)日：2022-10-18

申请号：US16842080

申请日：2020-04-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US11469225B2

公开(公告)日：2022-10-11

申请号：US17072649

申请日：2020-10-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/20 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US20220320015A1

公开(公告)日：2022-10-06

申请号：US17223596

申请日：2021-04-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Yusheng BIAN ,  Yves T. NGU ,  Sunil K. SINGH ,  Sebastian T. VENTRONE ,  Johnatan A. KANTAROVSKY

IPC: H01L23/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a backside structure for optical attack mitigation and methods of manufacture. The structure includes: at least one device on a front side of a semiconductor substrate; and a plurality of grating layers under the at least one device. The plurality of grating layers includes at least a first material having a first refractive index alternating with a second material having a second refractive index.

公开(公告)号：US20220311116A1

公开(公告)日：2022-09-29

申请号：US17211044

申请日：2021-03-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hanyi Ding

IPC: H01P3/08 ,  H01P11/00

Abstract: Structures for a microstrip transmission line and methods of forming a microstrip transmission line. The microstrip transmission line includes a signal line, a shield, and multiple wiring structures connected to the signal line. Each wiring structure extends from a portion of the signal line toward the shield, and each wiring structure includes a metal feature that is positioned adjacent to the shield.

公开(公告)号：US11448822B2

公开(公告)日：2022-09-20

申请号：US17131997

申请日：2020-12-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Yusheng Bian ,  Dali Shao

IPC: G02B6/12 ,  G02B6/122 ,  H01L29/06 ,  G02B6/30

Abstract: Disclosed is a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide. Also disclosed is a method for forming the SOI chip structure. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to a wafer bonding process that results in the SOI structure. Subsequently, front-end-of-the-line (FEOL) processing can be performed to form additional optical devices and/or electronic devices in and/or above the silicon layer. By embedding an optical waveguide within the substrate prior to wafer bonding as opposed to forming it during FEOL processing, strict limitations on the dimensions of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large such that the cut-off wavelength can be relatively long. Thus, such a substrate-embedded optical waveguide brings different functionality to the SOI chip structure as compared to FEOL optical waveguides.