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公开(公告)号：US20210151673A1
公开(公告)日：2021-05-20
申请号：US17100185
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Fabio Pellizzer
Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
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公开(公告)号：US20210005664A1
公开(公告)日：2021-01-07
申请号：US16460884
申请日：2019-07-02
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Paolo Fantini
Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.
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公开(公告)号：US10672981B2
公开(公告)日：2020-06-02
申请号：US16706358
申请日：2019-12-06
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US20200075858A1
公开(公告)日：2020-03-05
申请号：US16665955
申请日：2019-10-28
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20190362789A1
公开(公告)日：2019-11-28
申请号：US16419821
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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Patent Agency Ranking
公开(公告)号：US10461125B2
公开(公告)日：2019-10-29
申请号：US15689155
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Innocenzo Tortorelli
IPC: H01L27/24 , H01L45/00 , H01L27/115
Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
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公开(公告)号：US20190288194A1
公开(公告)日：2019-09-19
申请号：US16360756
申请日：2019-03-21
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20190051350A1
公开(公告)日：2019-02-14
申请号：US16158353
申请日：2018-10-12
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
CPC classification number: G11C13/0004 , G11C11/5678 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/008 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/16
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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公开(公告)号：US20190019949A1
公开(公告)日：2019-01-17
申请号：US16121433
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Giorgio Servalli , Carmela Cupeta , Fabio Pellizzer
CPC classification number: H01L45/1293 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
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公开(公告)号：US10157670B2
公开(公告)日：2018-12-18
申请号：US15338154
申请日：2016-10-28
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
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