公开(公告)号：US20250133719A1

公开(公告)日：2025-04-24

申请号：US18777365

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Christopher K. Morzano ,  Efe Sinan Ege

IPC: H10B12/00

Abstract: A variety of applications can include a memory device having an array of memory cells, with each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. Access lines can be coupled to gates of the GAA transistors and digit lines can be coupled to pillar channels of the GAA transistors. A lattice can be included between the access lines and the digit lines, where the lattice has dielectric regions between and contacting non-dielectric regions. Each non-dielectric region can be positioned on and contacting a digit line and can contain digit contact junctions to the pillar channels of a set of the GAA transistors extending from the non-dielectric region. Additional devices and methods are disclosed.

公开(公告)号：US12284798B2

公开(公告)日：2025-04-22

申请号：US17698558

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091

Abstract: A microelectronic device is disclosed that includes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices and extending in a first direction; and word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and the word lines extend into word line exit regions. The word line exit regions are horizontally alternating with the array regions in the second direction; and sub word line driver sections are overlapping and above, and in electrical communication with the word line exit regions. Electrical communication between word lines in the word line exit regions and the sub word line driver sections vertically coupled with a vertical word line contact and other interconnections is laterally bounded within socket regions delineated by horizontal boundaries of the word line exit regions.

公开(公告)号：US20250046723A1

公开(公告)日：2025-02-06

申请号：US18922192

申请日：2024-10-21

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Luoqi Li ,  Marsela Pontoh

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

Abstract: Semiconductor die assemblies with decomposable materials, and associated methods and systems are disclosed. In an embodiment, a semiconductor die assembly includes a memory controller die carrying one or more memory dies attached to its first side. The semiconductor die assembly also includes a biodegradable structure attached to its second side opposite to the first side. The biodegradable structure includes a conductive material and an insulating material, both of which are biodegradable and disintegrate in a wet process. The biodegradable structure can be configured to couple the memory controller die with an interface die. In this manner, when the biodegradable structure disintegrates (e.g., dissolve) in the wet process, the memory controller carrying the memory dies can be separated from the interface die to reclaim the memory controller with the memory dies and the interface die.

公开(公告)号：US20250015055A1

公开(公告)日：2025-01-09

申请号：US18891947

申请日：2024-09-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.

公开(公告)号：US12121381B2

公开(公告)日：2024-10-22

申请号：US17652910

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Yashvi Singh ,  Tanya Khatri ,  Fatma Arzum Simsek-Ege ,  Yanni Wang

IPC: A61B6/00 ,  A61B6/46

CPC classification number: A61B6/4405 ,  A61B6/4411 ,  A61B6/463 ,  A61B6/5205 ,  A61B6/5217 ,  A61B6/547 ,  A61B6/563

Abstract: In some implementations, a device may produce, via an x-ray module, x-rays to be directed towards a body part. The device may detect, via a sensor, the x-rays reflected from the body part. The device may generate, via the sensor, signals based on the x-rays reflected from the body part. The device may generate, via a processor, an x-ray image of the body part based on the first signals. The device may transmit the x-ray image to a server. The device may receive, from the server, a message that indicates a diagnosis associated with the x-ray image. The device may display, via a user interface, the x-ray image and information associated with the diagnosis associated with the x-ray image.

公开(公告)号：US20240215221A1

公开(公告)日：2024-06-27

申请号：US18522120

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A microelectronic device includes first memory array region and second memory array regions, each comprising vertical stacks of dynamic random access memory (DRAM) cells. A staircase region is between the first memory array region and the second memory array region and comprises a staircase structure comprising a vertical stack of first conductive structures horizontally extending through the staircase region in a first direction, the first conductive structures configured to be in contact with the DRAM cells of the first memory array region and DRAM cells of the second memory array region, and sub-staircase structures individually comprising second conductive structures horizontally extending from the vertical stack of first conductive structures in a second direction. Horizontally neighboring sub-staircase structures are substantially evenly horizontally spaced from one another in the first direction. Related microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240194671A1

公开(公告)日：2024-06-13

申请号：US18542240

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L27/06 ,  G11C5/06 ,  H01L21/8238 ,  H01L23/538 ,  H01L25/065 ,  H01L27/092

CPC classification number: H01L27/0688 ,  G11C5/06 ,  H01L21/8238 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/092

Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

公开(公告)号：US20240194256A1

公开(公告)日：2024-06-13

申请号：US18373490

申请日：2023-09-27

Applicant: Micron Technology, Inc.

Inventor： Brenton P. Van Leeuwen ,  Mingdong Cui ,  Fatma Arzum Simsek-Ege

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/0038

Abstract: Systems, methods and apparatus are provided for word line drivers for memory devices. For instance, an apparatus can include sets of word lines, each word line of the sets of word lines configured to access a respective set of one or more memory cells, sets of digit lines, where each word line couples a memory cell of the set of one or more memory cells with each digit line within the sets of digit lines, and a plurality of resistors coupled to the sets of word lines.

公开(公告)号：US11996377B2

公开(公告)日：2024-05-28

申请号：US17364335

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Beau D. Barry

IPC: H01L25/065 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  G11C11/4085 ,  G11C11/4091 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20240112724A1

公开(公告)日：2024-04-04

申请号：US17936760

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: G11C11/4091 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4091 ,  H01L25/0657 ,  H01L25/18

Abstract: Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.