公开(公告)号：US08912074B2

公开(公告)日：2014-12-16

申请号：US14329982

申请日：2014-07-13

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.

Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。

公开(公告)号：US20140322891A1

公开(公告)日：2014-10-30

申请号：US14329982

申请日：2014-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.

Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。

公开(公告)号：US08823132B2

公开(公告)日：2014-09-02

申请号：US13736082

申请日：2013-01-08

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/00

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US11482517B2

公开(公告)日：2022-10-25

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L21/3213 ,  H01L27/11582 ,  H01L49/02

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US11264488B2

公开(公告)日：2022-03-01

申请号：US16951361

申请日：2020-11-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092

Abstract: Provided is a manufacturing method of s semiconductor structure. The method includes: providing a substrate, wherein the substrate has a plurality of fin portions and at least one recessed portion, the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions; forming a doping layer on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion; and forming a dielectric layer on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

公开(公告)号：US10861673B2

公开(公告)日：2020-12-08

申请号：US16143419

申请日：2018-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01J37/302 ,  H01J37/317 ,  H01L21/027

Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

公开(公告)号：US10777556B2

公开(公告)日：2020-09-15

申请号：US16149125

申请日：2018-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/225 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

公开(公告)号：US10763175B2

公开(公告)日：2020-09-01

申请号：US16109667

申请日：2018-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US10707092B1

公开(公告)日：2020-07-07

申请号：US16245163

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Jhao-Hao Lee ,  Sho-Shen Lee ,  Chih-Yu Chiang

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L27/108

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

公开(公告)号：US10460997B2

公开(公告)日：2019-10-29

申请号：US16360019

申请日：2019-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/14 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/08 ,  H01L21/82 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.