公开(公告)号：US08111533B2

公开(公告)日：2012-02-07

申请号：US13190179

申请日：2011-07-25

Applicant: Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

Inventor： Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.

Abstract translation: 动态地调整诸如CAM设备的搜索引擎的功耗以防止由过热导致的性能下降和/或损坏。 对于一些实施例，CAM设备被连续采样以产生指示在每个采样周期期间执行的活动状态数量和比较操作数的采样信号。 累积采样信号以产生估计的设备功率分布，其与对应于预定功率电平的参考值进行比较，以产生指示由其功率消耗导致的设备的工作温度的预测增加的动态功率控制信号。 然后使用动态功率控制信号来选择性地降低CAM设备的输入数据速率，从而降低功耗并允许设备冷却。

公开(公告)号：US20120027029A1

公开(公告)日：2012-02-02

申请号：US13205420

申请日：2011-08-08

Applicant: Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

Inventor： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC: H04J99/00

CPC classification number: H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

Abstract: A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

Abstract translation: 提供了一种从软件中卸载数据包协议封装的方法。 在操作中，接收指针信息。 此外，使用指针信息，通过在硬件中组装分组，从软件卸载分组协议封装。

公开(公告)号：US08102936B2

公开(公告)日：2012-01-24

申请号：US11930978

申请日：2007-10-31

Applicant: Stefanos Sidiropoulos ,  Haw-Jyh Liaw

Inventor： Stefanos Sidiropoulos ,  Haw-Jyh Liaw

IPC: H04L25/34 ,  H04L27/14

CPC classification number: H04L7/0008 ,  H04L7/0337 ,  H04L25/068

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed. The data receiver circuit and the transmission line may be both fabricated on an integrated circuit, or the transmission line may be implemented external to the integrated circuit chip, such as on a package housing of the integrated circuit chip or on a printed circuit board for which the integrated circuit chip is mounted.

公开(公告)号：US08089794B1

公开(公告)日：2012-01-03

申请号：US12861084

申请日：2010-08-23

Applicant: Chetan Deshpande ,  Bindiganavale S. Nataraj

Inventor： Chetan Deshpande ,  Bindiganavale S. Nataraj

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value is being applied; and after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state.

Abstract translation: 响应于应用于多个比较单元电路的比较数据值，方法可以包括选择性地将结果行耦合到参考节点; 通过在应用比较数据值的同时启用第一预充电路径，将结果行预充电到预充电电位; 并且在通过启用第一预充电路径对结果行进行预充电之后，禁用第一预充电路径将其置于高阻抗状态。

公开(公告)号：US08089793B1

公开(公告)日：2012-01-03

申请号：US12195299

申请日：2008-08-20

Applicant: Nilesh A. Gharia

Inventor： Nilesh A. Gharia

IPC: G11C15/00

CPC classification number: G11C15/043

Abstract: A content addressable memory (CAM) cell includes a first storage element for storing a data value, a second storage element for storing the data value, and a compare circuit having first inputs to receive from the first storage element a first complementary data signal indicative of the data value, second inputs to receive from the second storage element a second complementary data signal indicative of the data value, third inputs to receive comparand data, and an output coupled to a match line. The CAM cell allows for simultaneous read and compare operations, as well as simultaneous refresh and compare operations.

Abstract translation: 内容可寻址存储器（CAM）单元包括用于存储数据值的第一存储元件，用于存储数据值的第二存储元件，以及具有第一输入的比较电路，用于从第一存储元件接收指示第一补充数据信号 所述数据值，从所述第二存储元件接收指示所述数据值的第二互补数据信号的第二输入，用于接收比较数据的第三输入和耦合到匹配线的输出。 CAM单元允许同时读取和比较操作，以及同步刷新和比较操作。

公开(公告)号：US08065456B2

公开(公告)日：2011-11-22

申请号：US12019576

申请日：2008-01-24

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F13/00 ,  G06F13/14 ,  G06F15/76

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface. The multiple-core processor has at least one of an internal fast messaging network or an interface switch interconnect configured to link the processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory. The fast messaging network or interface switch is also configured to be operably coupled to the star topology serial bus interface. In one aspect of an embodiment of the invention, the fast messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes.

Abstract translation: 高级处理器包括多个多线程处理器核，其被配置为支持多个软件产生的读取或写入指令，用于与星形拓扑串行总线接口进行接口。 多核处理器具有内部快速消息传递网络或配置成将处理器核心链接在一起的接口交换机互连中的至少一个，使得每个处理器核心具有到每个其他处理器核心的数据通路，而不经过存储器。 快速消息传递网络或接口交换机也被配置为可操作地耦合到星形拓扑串行总线接口。 在本发明的实施例的一个方面，快速消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。

公开(公告)号：US08059439B2

公开(公告)日：2011-11-15

申请号：US13169682

申请日：2011-06-27

Applicant: Kee Park

Inventor： Kee Park

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/1006 ,  G11C11/56 ,  G11C15/00

Abstract: An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM cell, data may be stored more efficiently and CAM systems may consume less power. The encoded data words can be balanced data words that have equal number of logic high and logic low values.

Abstract translation: 公开了一种编码方案，其允许CAM设备选择性地在CAM设备的行的每个单元内存储二进制值的单个位或从二进制值编码的编码数据字的两位。 通过在每个CAM单元中存储编码数据字的两个比特，可以更有效地存储数据，并且CAM系统可以消耗更少的功率。 编码数据字可以是具有相等数量的逻辑高和逻辑低值的平衡数据字。

公开(公告)号：US20110255542A1

公开(公告)日：2011-10-20

申请号：US13084516

申请日：2011-04-11

Applicant: David T. HASS ,  Abbas RASHID

Inventor： David T. HASS ,  Abbas RASHID

IPC: H04L12/56

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08031503B1

公开(公告)日：2011-10-04

申请号：US12822073

申请日：2010-06-23

Applicant: Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

Inventor： Carl Gyllenhammer ,  Greg Watson ,  Venkat Gaddam ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Chetan Deshpande

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.

Abstract translation: 动态地调整诸如CAM设备的搜索引擎的功耗以防止由过热导致的性能下降和/或损坏。 对于一些实施例，CAM设备被连续采样以产生指示在每个采样周期期间执行的活动状态数量和比较操作数的采样信号。 累积采样信号以产生估计的设备功率曲线，其与与预定功率水平相对应的参考值进行比较，以产生指示由其功耗引起的设备的工作温度的预测增加的动态功率控制信号。 然后使用动态功率控制信号来选择性地降低CAM设备的输入数据速率，从而降低功耗并允许设备冷却。

公开(公告)号：US08023300B1

公开(公告)日：2011-09-20

申请号：US12818555

申请日：2010-06-18

Applicant: Varadarajan Srinivasan ,  Chetan Deshpande ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

Inventor： Varadarajan Srinivasan ,  Chetan Deshpande ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Venkat Rajendher Reddy Gaddam

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner. More specifically, for CAM-based search engines configured according to present embodiments, the CAM array includes state information gating circuits that selectively allow state information stored in the CAM array's match latches to be transposed onto the array's bit lines and then read from the array using the array's sense amplifiers.

Abstract translation: 当前实施例允许搜索引擎通过以并行方式在搜索引擎和外部状态存储器之间传送状态信息来在多个数据流之间切换时，将状态信息快速地保存到外部状态存储器和从外部状态存储器恢复状态信息。 更具体地，对于根据本实施例配置的基于CAM的搜索引擎，CAM阵列包括状态信息门控电路，其选择性地允许存储在CAM阵列的匹配锁存器中的状态信息被转置到阵列的位线上，然后使用 阵列的读出放大器。