公开(公告)号：US11532616B2

公开(公告)日：2022-12-20

申请号：US16709753

申请日：2019-12-10

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US11532606B2

公开(公告)日：2022-12-20

申请号：US16806257

申请日：2020-03-02

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Jean-Michel Simonnet ,  Sophie Ngo ,  Simone Rascunà

IPC: H01L27/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20 ,  H01L29/417 ,  H01L29/868 ,  H02H9/04

Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20220393022A1

公开(公告)日：2022-12-08

申请号：US17730895

申请日：2022-04-27

Applicant: STMicroelectronics PTE LTD ,  STMicroelectronics (Tours) SAS

Inventor： Shin Phay LEE ,  Voon Cheng NGWAN ,  Frederic LANOIS ,  Fadhillawati TAHIR ,  Ditto ADNAN

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/66

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

公开(公告)号：US11515301B2

公开(公告)日：2022-11-29

申请号：US16353658

申请日：2019-03-14

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Aurelie Arnaud ,  Andrea Brischetto

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/861 ,  H02H9/04

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

公开(公告)号：US11451157B2

公开(公告)日：2022-09-20

申请号：US17071193

申请日：2020-10-15

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick Hague ,  Romain Launois

IPC: H02M7/162 ,  H02M1/00 ,  H02M7/06

Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.

公开(公告)号：US11387517B2

公开(公告)日：2022-07-12

申请号：US16255625

申请日：2019-01-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel

IPC: H01M10/00 ,  H01M50/209 ,  H02J7/02 ,  H01M10/46 ,  H01M10/04 ,  H01M10/42 ,  H01M10/44 ,  H01M50/10 ,  H01M50/116 ,  H01M50/124 ,  H01M50/502 ,  H01M6/40

Abstract: The disclosure relates to microbattery devices and assemblies. In an embodiment, a device includes a plurality of microbatteries, a first flexible encapsulation film, and a second flexible encapsulation film. Each of the microbatteries includes a first contact terminal and a second contact terminal spaced apart from one another. The first flexible encapsulation film includes a first conductive layer electrically coupled to the first contact terminal of each of the microbatteries, and a first insulating layer on the first conductive layer. The second flexible encapsulation film includes a second conductive layer electrically coupled to the second contact terminal of each of the microbatteries, and a second insulating layer on the second conductive layer.

公开(公告)号：US20220200472A1

公开(公告)日：2022-06-23

申请号：US17550534

申请日：2021-12-14

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick HAGUE ,  Benoit RENARD ,  Romain LAUNOIS

IPC: H02M7/162 ,  H02M1/36 ,  H02M1/32

Abstract: A voltage converter includes a circuit formed by a parallel association, connected between first and second nodes, of a first branch and a second branch. The first branch includes a first controlled rectifying element having a first impedance. The second branch includes a resistor associated in series with a second rectifying element having a second impedance substantially equal to the first impedance. The second rectifying element may, for example, be a triac having its gate coupled to receive a signal from an intermediate node in the series association of the second branch. Alternatively, the second rectifying element may be a thyristor having its gate coupled to receive a signal at the anode of the thyristor.

公开(公告)号：US20220190103A1

公开(公告)日：2022-06-16

申请号：US17542170

申请日：2021-12-03

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Mohamed BOUFNICHEL

IPC: H01L49/02

Abstract: The present description concerns a capacitor manufacturing method, including the successive steps of: a) forming a stack including, in the order from the upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer, and a second electrode; b) etching, by chemical plasma etching, an upper portion of the stack, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and c) etching, by physical plasma etching, a lower portion of the stack, said physical plasma etching being interrupted on the upper surface of the first conductive layer.

公开(公告)号：US11362084B2

公开(公告)日：2022-06-14

申请号：US17143703

申请日：2021-01-07

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud ,  Severine Lebrette

IPC: H01L27/00 ,  H01L27/02 ,  H01L21/22 ,  H01L29/66 ,  H01L29/866

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

公开(公告)号：US20220166340A1

公开(公告)日：2022-05-26

申请号：US17532717

申请日：2021-11-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick HAGUE ,  Romain LAUNOIS

IPC: H02M7/155 ,  H02M1/36 ,  H02M7/219

Abstract: A voltage converter delivers an output voltage between a first and a second node. The voltage converter includes a capacitor series-coupled with a resistor between the first and second nodes. The resistor is coupled in parallel with a bidirectional switch receiving at its control terminal a positive bias voltage referenced to the second node.