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    Apparatus and method to accelerate compression and decompression operations
    203.
    发明授权
    Apparatus and method to accelerate compression and decompression operations 有权
    加速压缩和减压操作的装置和方法

    公开(公告)号：US09294123B2

    公开(公告)日：2016-03-22

    申请号：US14595129

    申请日：2015-01-12

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: H03M7/34 ,  H03M7/30 ,  G06F9/30

    CPC classification number: H03M7/3086 ,  G06F9/30145 ,  G06F9/30178

    Abstract: Methods and apparatuses relating to an instruction to decode encoded information of a compression scheme are described. In one embodiment, a processor includes a decode unit to decode an instruction, and an execution unit to execute the instruction, the execution unit including a state machine and content addressable memory (CAM) circuitry, the state machine to receive a pointer to a stream of encoded information of a compression scheme, fetch a section of the encoded information, and apply the section of the encoded information to the CAM circuitry to obtain decoded information.

    Abstract translation: 描述与解码压缩方案的编码信息的指令相关的方法和装置。 在一个实施例中，处理器包括解码指令的解码单元和执行指令的执行单元，执行单元包括状态机和内容可寻址存储器（CAM）电路，状态机接收指向流的指针 的压缩方案的编码信息，获取编码信息的一部分，并将编码信息的部分应用于CAM电路以获得解码信息。

    SM3 HASH FUNCTION MESSAGE EXPANSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    205.
    发明申请
    SM3 HASH FUNCTION MESSAGE EXPANSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    SM3 HASH功能消息扩展处理器，方法，系统和指令

    公开(公告)号：US20150186139A1

    公开(公告)日：2015-07-02

    申请号：US14142745

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali ,  Sean Gulley

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30036 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/122

    Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj−16 XOR Wj−9 XOR(Wj−3

    Abstract translation: 处理器包括解码单元，用于接收指示第一源打包数据操作数和第二源打包数据操作数的指令。 每个源操作数包含元素。 数据元素包括从消息中选择的信息和足以评估的消息的逻辑组合：P1（Wj-16 XOR Wj-9 XOR（Wj-3 <<<15））XOR（Wj-13 <<<7） XOR Wj-6 P1是置换函数，P1（X）= X XOR（X <<<15）XOR（X <<< 23）。 Wj-16，Wj-9，Wj-3，Wj-13和Wj-6是与SM3散列函数的压缩函数相关联的消息。 XOR是异或运算。 <<<是旋转操作。 与解码单元耦合的执行单元，其可响应于该指令操作以将结果打包数据存储在目的地存储位置中。 结果打包数据以包括要输入到压缩函数的第j个的Wj消息。

    SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
    210.
    发明申请
    SYSTEM-ON-CHIP (SoC) TO PERFORM A BIT RANGE ISOLATION INSTRUCTION 审中-公开
    系统级芯片（SoC）执行位格式隔离指令

    公开(公告)号：US20150100761A1

    公开(公告)日：2015-04-09

    申请号：US14568754

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  ELMOUSTAPHA OULD-AHMED-VALL ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Abstract translation: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

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