公开(公告)号：US20210399929A1

公开(公告)日：2021-12-23

申请号：US17363132

申请日：2021-06-30

Applicant: Rambus Inc.

Inventor： Robert E. Palmer

IPC: H04L27/01 ,  H04L7/04 ,  H04L25/06 ,  H04L25/03

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

公开(公告)号：US11206020B2

公开(公告)日：2021-12-21

申请号：US16880208

申请日：2020-05-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  H03K19/0175 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20210375351A1

公开(公告)日：2021-12-02

申请号：US17323889

申请日：2021-05-18

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20210373811A1

公开(公告)日：2021-12-02

申请号：US17323024

申请日：2021-05-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G06F3/06

Abstract: A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

公开(公告)号：US11176037B2

公开(公告)日：2021-11-16

申请号：US16723361

申请日：2019-12-20

Applicant: Rambus Inc.

Inventor： Trung Am Diep ,  John Eric Linstadt

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/126 ,  G06F12/0891 ,  G06F12/1009 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

Abstract: Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.

公开(公告)号：US20210349250A1

公开(公告)日：2021-11-11

申请号：US17245320

申请日：2021-04-30

Applicant: Rambus Inc.

Inventor： Patrick R. Gill ,  David G. Stork

IPC: G02B5/30 ,  G02B5/18 ,  G02B27/46 ,  H04N5/335 ,  H01L27/146 ,  G02B27/42 ,  H04N5/232

Abstract: Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Images can be captured without a lens, and cameras can be made smaller than those that are reliant on lenses and ray-optical focusing.

公开(公告)号：US20210343318A1

公开(公告)日：2021-11-04

申请号：US17284433

申请日：2019-10-07

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Larry Grant Giddens

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4093

Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.

公开(公告)号：US20210326204A1

公开(公告)日：2021-10-21

申请号：US17106663

申请日：2020-11-30

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US20210311888A1

公开(公告)日：2021-10-07

申请号：US17306410

申请日：2021-05-03

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Larry Grant Giddens

IPC: G06F13/16 ,  G06F13/42

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

公开(公告)号：US11133081B2

公开(公告)日：2021-09-28

申请号：US17026133

申请日：2020-09-18

Applicant: Rambus Inc.

Inventor： Ashwin S. M. ,  Anirudha Shelke ,  Navin Kumar Mishra ,  Phalguni Bala ,  Younus Syed ,  Kiran Baby ,  Sudhir Kumar Katla Shetty

IPC: G11C7/10 ,  G11C29/36 ,  G11C7/22 ,  G11C29/50

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.