公开(公告)号：US20240397698A1

公开(公告)日：2024-11-28

申请号：US18789468

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H10B10/00 ,  H01L23/528

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

公开(公告)号：US20240396750A1

公开(公告)日：2024-11-28

申请号：US18790296

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Cormac Michael O'CONNELL

IPC: H04L9/32

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US20240395912A1

公开(公告)日：2024-11-28

申请号：US18790218

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Lin ,  Ming-Ho Lin ,  Chun-Heng Chen ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.

公开(公告)号：US20240395910A1

公开(公告)日：2024-11-28

申请号：US18788579

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Hsu ,  Yu-Chun Ko ,  Yu-Chang Liang ,  Kao-Ting Lai

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

公开(公告)号：US20240395906A1

公开(公告)日：2024-11-28

申请号：US18789520

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios VELLIANITIS

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming an isolation region on a top surface of a semiconductor substrate; etching a trench in the isolation region, wherein the trench extends along a first direction in a top view; growing an epitaxial structure in the trench; patterning the epitaxial structure to form a semiconductor fin orientated along a second direction in the top view, wherein an angle between the first and second directions is in a range from about 40 degrees to about 50 degrees; and forming a gate structure over the semiconductor fin.

公开(公告)号：US20240395902A1

公开(公告)日：2024-11-28

申请号：US18791056

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chih Lin ,  Yen-Ting Chen ,  Wen-Kai Lin ,  Szu-Chi Yang ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Ming-Lung Cheng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

公开(公告)号：US20240395875A1

公开(公告)日：2024-11-28

申请号：US18788591

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.

公开(公告)号：US20240395819A1

公开(公告)日：2024-11-28

申请号：US18791008

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/092 ,  G06F30/392

Abstract: A method includes placing, in a layout, a plurality of first cells each having a first NFET fin number. The first cells are swapped with a plurality of second cells each having a second NFET fin number less than the first NFET fin number. After swapping the first cells with the second cells, a timing critical path in the layout is identified. Some of the second cells in the identified timing critical path are swapped with a plurality of third cells each having a third NFET fin number greater than the second NFET fin number. After swapping some of the second cells in the identified timing critical path with the third cells, an integrated circuit is fabricated based on the layout.

公开(公告)号：US20240395795A1

公开(公告)日：2024-11-28

申请号：US18791291

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

IPC: H01L27/02 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

公开(公告)号：US20240395776A1

公开(公告)日：2024-11-28

申请号：US18790261

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Haohua Zhou ,  Mei Hsu Wong ,  Tze-Chiang Huang

IPC: H01L25/065 ,  H01L23/525 ,  H03K5/24 ,  H03K19/20

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.