公开(公告)号：US20210294531A1

公开(公告)日：2021-09-23

申请号：US17235629

申请日：2021-04-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F3/06 ,  G11C5/04 ,  G06F13/16

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US20210232203A1

公开(公告)日：2021-07-29

申请号：US17117388

申请日：2020-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US11068017B2

公开(公告)日：2021-07-20

申请号：US15863703

申请日：2018-01-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/04 ,  G06F1/08 ,  G11C7/02 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G06F1/10 ,  G06F1/06 ,  G06F1/12

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US11049532B2

公开(公告)日：2021-06-29

申请号：US15721755

申请日：2017-09-30

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20210091862A1

公开(公告)日：2021-03-25

申请号：US17024835

申请日：2020-09-18

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/11 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04B17/21 ,  H04B17/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

公开(公告)号：US20210073122A1

公开(公告)日：2021-03-11

申请号：US17065082

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1009

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US10901485B2

公开(公告)日：2021-01-26

申请号：US16418259

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/12 ,  G06F13/36 ,  G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0855

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20200371868A1

公开(公告)日：2020-11-26

申请号：US16872929

申请日：2020-05-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/10 ,  G06F11/16 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/52 ,  G11C29/00 ,  H03M13/15

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US10811080B2

公开(公告)日：2020-10-20

申请号：US16215275

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L7/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H01L27/11582

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US10810139B2

公开(公告)日：2020-10-20

申请号：US16266526

申请日：2019-02-04

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.