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    SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE
    223.
    发明公开
    SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230214133A1

    公开(公告)日：2023-07-06

    申请号：US18090449

    申请日：2022-12-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Jeffrey S. McNeil ,  Niccolo' Righetti ,  Silvia Beltrami ,  Violante Moschiano ,  Ugo Russo

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

    Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

    MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION AND A CONTROL LOGIC REGION
    225.
    发明申请
    MICROELECTRONIC DEVICES HAVING A MEMORY ARRAY REGION AND A CONTROL LOGIC REGION 有权

    公开(公告)号：US20230092320A1

    公开(公告)日：2023-03-23

    申请号：US18059165

    申请日：2022-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

    IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582

    Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

    SACRIFICIAL STRINGS IN A MEMORY DEVICE TO DETECT READ DISTURB
    226.
    发明申请
    SACRIFICIAL STRINGS IN A MEMORY DEVICE TO DETECT READ DISTURB 有权

    公开(公告)号：US20230060440A1

    公开(公告)日：2023-03-02

    申请号：US17877411

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Eric N. Lee

    IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4072

    Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array of the memory device, the block comprising a plurality of wordlines, wherein each of the plurality of memory strings comprises a plurality of memory cells associated with the plurality of wordlines, and wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines of the memory array concurrently and senses a level of current flowing through the first memory string designated as the sacrificial string while the read voltage is applied to each of the plurality of wordline. In addition, the control logic identifies, based on the level of current flowing through the first memory string designated as the sacrificial string, whether a threshold level of read disturb has occurred on the block.

    PROGRAMMING MEMORY CELLS OF MEMORY DEVICES
    229.
    发明申请
    PROGRAMMING MEMORY CELLS OF MEMORY DEVICES 有权

    公开(公告)号：US20220208261A1

    公开(公告)日：2022-06-30

    申请号：US17688983

    申请日：2022-03-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

    Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

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