STIMULATION LEAD AND METHOD INCLUDING A MULTI-DIMENSIONAL ELECTRODE ARRAY

    公开(公告)号:US20240091529A1

    公开(公告)日:2024-03-21

    申请号:US18521076

    申请日:2023-11-28

    CPC classification number: A61N1/0553 A61N1/05 A61N1/0551 A61N1/0556

    Abstract: Stimulation lead includes an elongated lead body having distal and proximal ends and wire conductors extending therebetween. The stimulation lead also includes a lead paddle having a multi-dimensional array of electrodes positioned along a contact side of the lead paddle. The electrodes are electrically coupled to the wire conductors. The lead paddle includes a paddle body and a conductor organizer disposed within the paddle body. The conductor organizer has multiple channels extending along the lead paddle. The channels receive the wire conductors and retain the wire conductors in a designated arrangement with respect to the lead paddle. The conductor organizer has openings to the channels. The wire conductors extend through the openings and are terminated to the respective electrodes.

    NEUROSTIMULATION SYSTEM
    234.
    发明公开

    公开(公告)号:US20240033529A1

    公开(公告)日:2024-02-01

    申请号:US18342412

    申请日:2023-06-27

    Inventor: Daran DeShazo

    CPC classification number: A61N1/36175 A61N1/37252

    Abstract: Provided is an implantable pulse generator (IPG) that includes a controller, and stimulation circuitry for generating electrical pulses to stimulate neural tissue of the patient. The IPG also includes a static random-access memory (SRAM) component for storing data to control the generating of the electrical pulses, wherein the SRAM component is connected to at least the controller through a first interface bus at a first word width and is connected to at least the stimulation circuitry through a second interface bus at a second word width. The SRAM component comprises column select logic that decodes read or write (R/W) access from the controller and provides for selective connection of each column of the SRAM component to the first interface bus during the R/W access, or to the second interface bus during stimulation operations to provide stimulation control data to components of the stimulation circuitry.

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