公开(公告)号：US20190391869A1

公开(公告)日：2019-12-26

申请号：US16013710

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US10509651B2

公开(公告)日：2019-12-17

申请号：US15388642

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Vinodh Gopal

IPC: G06F9/302 ,  G06F9/34 ,  G06F7/72 ,  G06F7/52 ,  G06F9/30 ,  G06F9/35 ,  G06F7/544

Abstract: A processor of an aspect includes a plurality of registers, and a decode unit to decode an instruction. The instruction is to indicate at least one storage location that is to store a first integer, a second integer, and a modulus. An execution unit is coupled with the decode unit, and coupled with the plurality of registers. The execution unit, in response to the instruction, is to store a Montgomery multiplication product corresponding to the first integer, the second integer, and the modulus, in a destination storage location. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US10404836B2

公开(公告)日：2019-09-03

申请号：US15390579

申请日：2016-12-26

Applicant: Intel Corporation

Inventor： James D. Guilford ,  Vinodh Gopal ,  Daniel F. Cutter

IPC: H04L29/06

Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.

公开(公告)号：US20190245679A1

公开(公告)日：2019-08-08

申请号：US15887290

申请日：2018-02-02

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sanu K. Matthew ,  Sudhir K. Satpathy ,  Vinodh Gopal

IPC: H04L9/06 ,  G09C1/00

Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X−1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.

公开(公告)号：US20190205093A1

公开(公告)日：2019-07-04

申请号：US15857281

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vinodh Gopal

IPC: G06F7/523 ,  G06F7/72

CPC classification number: G06F7/523 ,  G06F7/724

Abstract: In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.

公开(公告)号：US10331451B2

公开(公告)日：2019-06-25

申请号：US15396572

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F21/60 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G09C1/00 ,  H04L9/32 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US10331450B2

公开(公告)日：2019-06-25

申请号：US15396563

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F21/60 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G09C1/00 ,  H04L9/32 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20190182032A1

公开(公告)日：2019-06-13

申请号：US16208542

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: H04L9/06 ,  G06F15/80 ,  G06F21/60 ,  G06F21/64 ,  G06F9/30 ,  G06F9/38

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

公开(公告)号：US10313107B2

公开(公告)日：2019-06-04

申请号：US14984616

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G Dixon ,  Srinivas Chennupaty ,  Michael E Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US10270589B2

公开(公告)日：2019-04-23

申请号：US14572607

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: G06F21/72 ,  H04L9/28 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.