公开(公告)号：US11205650B2

公开(公告)日：2021-12-21

申请号：US16583406

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

公开(公告)号：US20210376093A1

公开(公告)日：2021-12-02

申请号：US17016109

申请日：2020-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

公开(公告)号：US20210376081A1

公开(公告)日：2021-12-02

申请号：US17402985

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L21/762 ,  H01L29/10

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US20210375864A1

公开(公告)日：2021-12-02

申请号：US16888537

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20210375859A1

公开(公告)日：2021-12-02

申请号：US16888380

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Kuan-Ting Pan ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/306

Abstract: According to one example, a method includes performing a Chemical Mechanical Polishing (CMP) process on a semiconductor workpiece that includes a nanosheet region, the nanosheet region having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes stopping the CMP process when the first type of semiconductor material is covered by the second type of semiconductor material, patterning the nanosheet region to form nanosheet stacks, forming an isolation structure around the nanosheet stacks, removing a top layer of the second type of semiconductor material from the nanosheet stacks, recessing the isolation structure, and forming a gate structure over the nanosheet stacks.

公开(公告)号：US20210359142A1

公开(公告)日：2021-11-18

申请号：US17097323

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

公开(公告)号：US20210343716A1

公开(公告)日：2021-11-04

申请号：US17376397

申请日：2021-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Guan-Lin Chen ,  Ting-Hung Hsu ,  Jiun-Jia Huang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417

Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

公开(公告)号：US20210336033A1

公开(公告)日：2021-10-28

申请号：US16858440

申请日：2020-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

Abstract: A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.

公开(公告)号：US11152477B2

公开(公告)日：2021-10-19

申请号：US16802275

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3205 ,  H01L29/06

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

公开(公告)号：US20210305428A1

公开(公告)日：2021-09-30

申请号：US17081894

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.