公开(公告)号：US20190027589A1

公开(公告)日：2019-01-24

申请号：US15655881

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/465 ,  H01L29/7869

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

公开(公告)号：US20190027410A1

公开(公告)日：2019-01-24

申请号：US16143368

申请日：2018-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction. A total height of the gate isolation structure is greater than a height of the shallow trench isolation structure formed on the semiconductor substrate and located between the fin structures.

公开(公告)号：US20190019805A1

公开(公告)日：2019-01-17

申请号：US15987919

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Cheng Tung

IPC: H01L27/11573 ,  H01L27/105

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.

公开(公告)号：US10169521B2

公开(公告)日：2019-01-01

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/00 ,  G06F17/50 ,  H01L27/02 ,  H01L27/108

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US10121704B2

公开(公告)日：2018-11-06

申请号：US15861692

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L21/70 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

公开(公告)号：US10103150B1

公开(公告)日：2018-10-16

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US20180294266A1

公开(公告)日：2018-10-11

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US10090203B2

公开(公告)日：2018-10-02

申请号：US15604675

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US20180240705A1

公开(公告)日：2018-08-23

申请号：US15472295

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L21/76895 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/528 ,  H01L23/535 ,  H01L27/10888 ,  H01L29/0649

Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US20180211960A1

公开(公告)日：2018-07-26

申请号：US15925780

申请日：2018-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/092 ,  H01L29/267 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/30625 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/267

Abstract: A semiconductor device includes a substrate having a first region and a second region, a fin-shaped structure and a bump on the first region of the substrate, and a shallow trench isolation (STI) around the fin-shaped structure and on the bump. Preferably, the fin-shaped structure and the bump comprise different material, the fin-shaped structure comprises a top portion and a bottom portion, the top portion and the bottom portion comprise different semiconductor material, and a top surface of the bottom portion is lower than a top surface of all of the STI on both the first region and the second region and higher than a top surface of the bump and the top surface of the bump contacts the STI directly.