公开(公告)号：US20030158882A1

公开(公告)日：2003-08-21

申请号：US10322197

申请日：2002-12-17

Applicant: STMicroelectronics Limited

Inventor： Simon Knowles

IPC: G06F007/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (mnull2) of logical stages is nnull2mnull1 and for bit lengths n not of a binary order, the number (mnull2) of logical stages is nbonull2mnull1, where nbo is the next largest binary order after n.

Abstract translation: 描述了根据该方法设计的加法电路的设计方法和加法电路。 优化设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数和通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。 对于位长度n，逻辑级数（m + 2）为n = 2m + 1，对于不是二进制顺序的位长度n，逻辑级的数量（m + 2）为nbo = 2m + 1，其中 nbo是n之后的下一个最大的二进制顺序。

公开(公告)号：US20030140338A1

公开(公告)日：2003-07-24

申请号：US10206381

申请日：2002-07-26

Applicant: STMicroelectronics Limited

Inventor： Antony Bowers ,  Richard Shann

IPC: G06F009/44

CPC classification number: G06F8/54

Abstract: Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions that describe how the current call frame changes during execution of each function. Described herein is a means of generating call frame information at link time, using linker macro calls generated by a small set of assembler macros.

Abstract translation: 呼叫帧信息由调试软件使用。 它记录了在执行程序期间的任何时候如何恢复父堆栈帧。 它通常在编译期间生成并以压缩格式存储在可执行文件中，该格式由描述当前调用帧在每个功能执行期间如何改变的指令序列组成。 这里描述的是使用由一组汇编器宏生成的链接器宏调用在链接时产生呼叫帧信息的手段。

公开(公告)号：US20030068000A1

公开(公告)日：2003-04-10

申请号：US10247263

申请日：2002-09-18

Applicant: STMicroelectronics Limited

Inventor： Robert Geoffrey Warren

IPC: G06F003/00 ,  H04L007/00

CPC classification number: G01R31/318552 ,  G01R31/31937

Abstract: A system comprising a host, a target and connection means therebetween. The host has means for providing a clock signal, first output means for outputting said clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said clock signal, said target having first input means for receiving said clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means. The host further comprises input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and controlling the clocking in of said data received from said target in dependence on said oversampling.

Abstract translation: 一种包括主机，目标和它们之间的连接装置的系统。 主机具有用于提供时钟信号的装置，用于经由所述连接装置将所述时钟信号输出到所述目标的第一输出装置和用于经由所述连接装置将数据输出到所述目标的第二输出装置，所述数据由所述时钟信号输出， 所述目标具有用于从所述主机接收所述时钟信号的第一输入装置，用于从所述主机接收所述数据的第二输入装置和用于经由所述连接装置向所述主机输出数据的第一输出装置。 主机还包括用于从所述目标接收所述数据的输入装置，以及过采样装置，用于对来自目标的接收数据进行过采样，并根据所述过采样来控制从所述目标接收的所述数据的时钟。

公开(公告)号：US20030016836A1

公开(公告)日：2003-01-23

申请号：US10147436

申请日：2002-05-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: H04B015/00

CPC classification number: H03G3/345 ,  H03G3/34

Abstract: A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio signal prior to its application to the input node, and a further bipolar transistor is connected between the FET and the output node for raising the voltage level of the audio signal prior to its application to the output node. This serves to maintain the DC bias level of the audio output signal independently of the status of the mute control signal.

Abstract translation: 一种静音开关，包括场效应晶体管，在其栅极处接收静音控制信号，用于选择性地将音频信号从输入节点提供给输出节点。 双极晶体管连接在输入节点和FET之间，用于在施加到输入节点之前降低音频信号的电压电平，并且在FET和输出节点之间连接另外的双极晶体管，以提高电压电平 该音频信号在其应用于输出节点之前。 这用于独立于静音控制信号的状态来维持音频输出信号的DC偏置电平。

公开(公告)号：US20030011592A1

公开(公告)日：2003-01-16

申请号：US10133971

申请日：2002-04-26

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Magne Sandven

IPC: G06T017/00

CPC classification number: G06T15/005

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract translation: 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

公开(公告)号：US20020171459A1

公开(公告)日：2002-11-21

申请号：US10104994

申请日：2002-03-22

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03K021/00

CPC classification number: H03K23/68 ,  H03K23/546

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract translation: 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。

公开(公告)号：US20020131298A1

公开(公告)日：2002-09-19

申请号：US10085987

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： William Bryan Barnes

IPC: G11C011/34

CPC classification number: H03K5/249 ,  G11C7/065 ,  H03K3/356139 ,  H03K5/1534 ,  H03K19/0963

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract translation: 为了确定预充电节点是否保持隔离或者可替代地进行放电，常规电路允许不确定性。 在评估开始一段时间后，常规电路将给出一个可能随后证明是错误的初步结果。 评估过程中耗电。 差分偏移动态比较器和定时电路用于评估节点是否正在放电。 由于比较器具有偏移，因此可以感测到与预充电电位相差较小的偏差：因为它是动态的，所以它不消耗稳态电流。 定时电路可以准确了解何时查看输出：在定时周期过去之前，已知结果无效。

公开(公告)号：US6018274A

公开(公告)日：2000-01-25

申请号：US669007

申请日：1996-06-21

Applicant: Philip G. Mattos ,  Mark A. Beach

Inventor： Philip G. Mattos ,  Mark A. Beach

IPC: H03B25/00 ,  H03D3/00 ,  H03B5/12 ,  H03B5/18 ,  H03B5/36

CPC classification number: H03B25/00 ,  H03D3/006

Abstract: The present invention relates to a radio receiver, particularly to a receiver for use in single-frequency applications, such as GPS, and to a frequency generator, which may be used in such a radio receiver, or elsewhere. The frequency generator comprises a tuned circuit connected between the emitter of the transistor and ground, such that a voltage signal at the basic frequency appears on the emitter terminal of the transistor. This arrangement has the advantage that the two frequencies appear on separate ports, and provides a radio receiver including radio receiver circuitry for connection to digital signal processing circuitry, reducing the complexity of the overall circuit. Additionally, there is a radio receiver wherein separate first and second local oscillator signals are generated from the terminal of s single transistor, avoiding the need for cascade multiplication stages, again reducing the size and complexity of the overall circuit. Further, circuitry is included generating an oscillator signal whereby the signal processing means tolerates the resulting frequency errors, and a single frequency direct downconversion receiver, comprising means for sub-sampling and one-bit coding the demodulated signal, and a transistor capable of decoding a microwave local oscillator signal and a digital signal processor with a clock signal for tolerating frequency errors.

Abstract translation: 无线电接收机技术领域本发明涉及一种无线电接收机，特别涉及用于诸如GPS的单频应用的接收机，以及可用于这种无线电接收机或其他地方的频率发生器。 频率发生器包括连接在晶体管的发射极和地之间的调谐电路，使得在晶体管的发射极端子出现基频的电压信号。 这种布置具有这样的优点：两个频率出现在分开的端口上，并且提供一种无线电接收机，包括用于连接到数字信号处理电路的无线电接收机电路，从而降低整个电路的复杂性。 此外，存在无线电接收机，其中从单个晶体管的端子产生分离的第一和第二本地振荡器信号，避免了对级联乘法级的需要，从而再次降低了整个电路的尺寸和复杂性。 此外，包括产生振荡器信号的电路，由此信号处理装置容忍所得到的频率误差，以及包括用于对解调信号进行子采样和一比特编码的装置的单频直接下变频接收机，以及能够对 微波本地振荡器信号和数字信号处理器，具有允许频率误差的时钟信号。