公开(公告)号：US20150055427A1

公开(公告)日：2015-02-26

申请号：US13972725

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/76 ,  G11C29/802 ,  H03M13/13 ,  H03M13/19

Abstract: An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

公开(公告)号：US20150055395A1

公开(公告)日：2015-02-26

申请号：US13972414

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/7807 ,  G06F17/5054

Abstract: An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored.

公开(公告)号：US08933725B2

公开(公告)日：2015-01-13

申请号：US13963446

申请日：2013-08-09

Applicant: Via Technologies, Inc.

Inventor： Hung-Yi Kuo

IPC: H03K19/173 ,  H03K19/0175

CPC classification number: H03K19/017581

Abstract: A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal.

Abstract translation: 提供了在多种状态之间切换的状态机电路。 状态机电路具有：状态补丁电路，用于根据当前状态值和第二输入信号，预测状态值和第二输入信号中的至少一个产生修补预测状态值，修补输出值和选择信号 状态机电路的输出值; 第一选择电路，用于根据选择信号将修补的预测状态或预测状态输出到寄存器; 以及第二选择电路，用于根据选择信号输出修补的输出值或输出值，其中根据第一输入信号和状态机电路的当前状态值产生预测状态值和输出值，以及 根据第二输入信号不产生预测状态值和输出值。

公开(公告)号：US20140361823A1

公开(公告)日：2014-12-11

申请号：US14202288

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G06F1/26 ,  G06F1/3243 ,  H03K19/0008 ,  Y02D10/152

Abstract: A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.

Abstract translation: 可以在包括全局电源总线，门控电源总线，从门控电源总线接收电压的功能电路以及数字电源门控系统的集成电路上实现的系统。 数字电源门控系统包括门控设备，电源门控控制系统和全局控制调节器。 门控设备耦合在全局和门控供电总线之间，并由数字控制值控制。 电源门控控制系统通过连续调整数字控制值来执行电源门控，以将门控电源总线的电压降低到状态保持电压电平。 全局控制调节器执行数字控制值的全局调整，以增加门控电源总线的电压，以防止其响应于全局电源总线的电压即将发生变化而降低到状态保持电压电平以下。

公开(公告)号：US20140351561A1

公开(公告)日：2014-11-27

申请号：US14066520

申请日：2013-10-29

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Terry Parks ,  G. Glenn Henry

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836

Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

Abstract translation: 微处理器包括指令翻译单元，其从IT指令中提取条件信息，并使IT指令与第一IT块指令融合。 对于IT块的每个指令，指令转换单元使用从IT指令提取的条件信息来确定IT块指令的相应条件，并将IT块指令转换成微指令。 微指令包括各自的条件。 执行单元根据各自的条件有条件地执行微指令。 对于每个IT块指令，指令转换单元使用提取的条件信息来确定各自的状态值。 状态值包括具有左移N-1位的低5位的IT指令的低8位，其中N表示IT块指令在IT块中的位置。

公开(公告)号：US08886960B2

公开(公告)日：2014-11-11

申请号：US14066485

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  H04L9/08 ,  G06F12/08 ,  G06F21/52 ,  G06F21/71 ,  G06F21/72 ,  G06F9/30 ,  G06F21/60 ,  H04L9/06 ,  G06F21/54

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set.

Abstract translation: 微处理器包括具有一定位的架构化寄存器。 微处理器设置位。 微处理器还包括提取单元，其响应于微处理器设置该位，从指令高速缓存取出加密指令并在执行它们之前对其进行解密。 微处理器将该位的值保存到存储器中的堆栈，然后清除该位，以响应接收到中断。 提取单元从指令高速缓存中读取未加密的指令，并在微处理器清零位之后执行它们而不对其进行解密。 微处理器将保存的值从存储器中的堆栈恢复到架构化寄存器中的位，以响应执行中断指令的返回。 响应于确定该位的恢复值被设置，获取单元恢复获取和解密加密指令。

公开(公告)号：US08880902B2

公开(公告)日：2014-11-04

申请号：US14066428

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  H04L9/08 ,  G06F12/08 ,  G06F21/52 ,  G06F21/71 ,  G06F21/72 ,  G06F9/30 ,  G06F21/60 ,  H04L9/06 ,  G06F21/54

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data.

Abstract translation: 微处理器具有用于将加密指令数据解密为明文指令数据并安全执行该方法。 微处理器包括一个包含多个主密钥的主密钥寄存器文件。 微处理器中的选择逻辑电路选择多个主键中的至少两个的组合。 微处理器中的密钥扩展电路对所选择的主密钥执行数学运算，以产生具有长的有效密钥长度的解密密钥。 指令解密电路对加密指令数据和解密密钥进行有效的数学运算，将加密指令数据解密为明文指令数据。

公开(公告)号：US08879345B1

公开(公告)日：2014-11-04

申请号：US13972768

申请日：2013-08-21

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/785 ,  G11C29/802

Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract translation: 一种装置包括半导体熔丝阵列和多个芯。 半导体熔丝阵列设置在芯片上，其中是编程配置数据。 阵列具有第一多个保险丝和第二多个保险丝。 第一组多个保险丝以编码和压缩格式存储配置数据。 第二多个保险丝存储第一压缩熔丝校正数据，其指示与其先前存储的状态将改变其状态的第一多个保险丝内的第一个或多个保险丝对应的位置和值。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到阵列，并且在加电/复位期间访问所有压缩的配置数据，以用于初始化多个芯内的元件。

公开(公告)号：US08878580B1

公开(公告)日：2014-11-04

申请号：US14030560

申请日：2013-09-18

Applicant: VIA Technologies, Inc.

Inventor： Darius D. Gaskins ,  James R. Lundberg

IPC: H03L7/06

CPC classification number: H03L7/22

Abstract: A clock system receiving a reference clock signal via an alignment location and developing a functional clock signal provided to a functional circuit via a clock path. The clock system includes a low bandwidth PLL, a high bandwidth PLL, and a delay path. The low bandwidth PLL receives the reference clock signal and a feedback clock signal and provides a filtered clock signal. The high bandwidth PLL receives the filtered clock signal and provides the functional clock signal, and has a feedback input coupled to its output via a local feedback path. The delay path is coupled between the output of the low bandwidth PLL and the alignment location to provide the feedback clock signal to the low bandwidth PLL. The delay and clock paths are substantially matched. The bandwidths of the low and high bandwidth PLLs may be individually configured to reduce both input jitter and internal jitter, respectively.

Abstract translation: 时钟系统经由对准位置接收参考时钟信号，并且经由时钟路径开发提供给功能电路的功能时钟信号。 时钟系统包括低带宽PLL，高带宽PLL和延迟路径。 低带宽PLL接收参考时钟信号和反馈时钟信号，并提供滤波后的时钟信号。 高带宽PLL接收经滤波的时钟信号并提供功能时钟信号，并具有通过本地反馈路径耦合到其输出的反馈输入。 延迟路径耦合在低带宽PLL的输出和对准位置之间，以将反馈时钟信号提供给低带宽PLL。 延迟和时钟路径基本匹配。 低带宽和高带宽PLL的带宽可以单独配置为分别减少输入抖动和内部抖动。

公开(公告)号：US20140306966A1

公开(公告)日：2014-10-16

申请号：US13933276

申请日：2013-07-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Hung-Yi KUO ,  Chia-Hung SU

IPC: G09G5/12

CPC classification number: G09G5/12 ,  G06F3/1446 ,  G09G2300/026 ,  G09G2370/022

Abstract: A video wall, having screens, cables, synchronization detection modules and a central control unit. The cables are operative to carry image data to be displayed on the screens. The synchronization detection modules are coupled between the screens and the cables for detection of a feature symbol. The central control unit collects detection results from the synchronization detection modules, and the detection results are utilized in the adjustment of the image data before cable transmission. In this manner, image display synchronization between the screens is achieved. The synchronization detection modules may be implemented as connectors, each having a first end connected to a screen and a second end connected to a cable.

Abstract translation: 具有屏幕，电缆，同步检测模块和中央控制单元的视频墙。 电缆可操作以携带要显示在屏幕上的图像数据。 同步检测模块耦合在屏幕和电缆之间，用于检测特征符号。 中央控制单元收集同步检测模块的检测结果，检测结果用于电缆传输前图像数据的调整。 以这种方式，实现了屏幕之间的图像显示同步。 同步检测模块可以实现为连接器，每个连接器具有连接到屏幕的第一端和连接到电缆的第二端。