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    Asymmetric multi-core processor with native switching mechanism
    1.
    发明授权
    Asymmetric multi-core processor with native switching mechanism 有权

    公开(公告)号：US10423216B2

    公开(公告)日：2019-09-24

    申请号：US14077740

    申请日：2013-11-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

    IPC: G06F9/46 ,  G06F1/3293 ,  G06F9/50

    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

    Compressing instruction queue for a microprocessor
    2.
    发明授权
    Compressing instruction queue for a microprocessor 有权

    公开(公告)号：US10216520B2

    公开(公告)日：2019-02-26

    申请号：US14569313

    申请日：2014-12-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Matthew Daniel Day ,  G. Glenn Henry ,  Terry Parks

    IPC: G06F9/38

    Abstract: A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.

    MULTI-CORE SYNCHRONIZATION MECHANISM
    4.
    发明申请
    MULTI-CORE SYNCHRONIZATION MECHANISM 有权
    多核同步机制

    公开(公告)号：US20150067369A1

    公开(公告)日：2015-03-05

    申请号：US14281434

    申请日：2014-05-19

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

    Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

    Abstract translation: 微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。 每个处理核心被配置为分别向控制单元写入一个值。 对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。 控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。 控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM
    7.
    发明申请
    ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM 有权
    不对称多核心处理器与本地切换机制

    公开(公告)号：US20140298060A1

    公开(公告)日：2014-10-02

    申请号：US14077740

    申请日：2013-11-12

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Terry Parks ,  G. Glenn Henry

    IPC: G06F1/32

    Abstract: A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

    Abstract translation: 处理器包括被配置为支持其指令集体系结构（ISA）特征集的特征的第一和第二相应子集的第一和第二处理核心。 第一个子集小于ISA功能集的所有功能。 第一个和第二个子集是不同的，但它们的联合是ISA功能集的所有功能。 第一核心在由第一核心而不是第二核心执行的同时检测线程，尝试使用不在第一子集中的特征，并且响应地指示从第一核到第二核的切换以执行 线程。 不支持的功能可能是不支持的指令或操作模式。 如果较低性能/功率核心被过度利用或较高性能/功率核心利用不足，也可能产生开关。

    REVOKEABLE MSR PASSWORD PROTECTION
    8.
    发明申请
    REVOKEABLE MSR PASSWORD PROTECTION 有权
    可靠的MSR密码保护

    公开(公告)号：US20140059358A1

    公开(公告)日：2014-02-27

    申请号：US14053953

    申请日：2013-10-15

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F12/14

    CPC classification number: G06F12/1408 ,  G06F9/30076 ,  G06F9/30101 ,  G06F21/31 ,  G06F21/71 ,  G06F21/78 ,  G06F21/79

    Abstract: A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.

    Abstract translation: 微处理器包括具有地址的型号特定寄存器（MSR），具有第一预定值制造的保险丝和控制寄存器。 微处理器首先将第一预定值从保险丝加载到控制寄存器中。 在最初将第一预定值加载到控制寄存器之后，微处理器还从包括微处理器的计算机系统的系统软件接收第二预定值。 微处理器通过提供通过利用在微处理器的第一实例中制造的秘密密钥加密第一预定值和MSR地址的功能产生的第一密码的指令来禁止对MSR的访问，并使得能够通过指令访问MSR 其提供通过用秘密密钥加密第二预定值的功能和MSR地址产生的第二密码。

    Running state power saving via reduced instructions per clock operation
    10.
    发明授权
    Running state power saving via reduced instructions per clock operation 有权
    通过每个时钟操作减少指令来运行状态省电

    公开(公告)号：US09442732B2

    公开(公告)日：2016-09-13

    申请号：US13777104

    申请日：2013-02-26

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F9/30 ,  G06F1/32

    CPC classification number: G06F9/30189 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/24

    Abstract: A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.

    Abstract translation: 微处理器包括可写的功能单元和控制寄存器，以使功能单元执行动作，以减少微处理器的每时钟指令速率，以在微处理器以最低性能运行状态运行时降低功耗。 这些操作的示例包括按顺序执行，无序执行，串行与并行缓存访问以及每个时钟周期中的单个或多个指令发出，退出，转换和/或格式化。 只有在存在附加条件的情况下，才能设置动作，例如最低运行时间停留在最低运行状态，不超过最长时间运行在较高的运行状态，用户没有禁用该功能，微处理器支持 多个运行状态和操作系统支持多个运行状态。

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