公开(公告)号：US20210083067A1

公开(公告)日：2021-03-18

申请号：US16571715

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tsung Wang ,  Lin-Yu Huang ,  Chia-Lin Chuang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28 ,  H01L21/764 ,  H01L29/66

Abstract: A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.

公开(公告)号：US20200111702A1

公开(公告)日：2020-04-09

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8234

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US20190244897A1

公开(公告)日：2019-08-08

申请号：US16384027

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.

公开(公告)号：US20190096809A1

公开(公告)日：2019-03-28

申请号：US15938258

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Wayne Lai

IPC: H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US10026647B2

公开(公告)日：2018-07-17

申请号：US15498259

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US09875967B2

公开(公告)日：2018-01-23

申请号：US15464759

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US20170194259A1

公开(公告)日：2017-07-06

申请号：US15464759

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US09633897B2

公开(公告)日：2017-04-25

申请号：US15170059

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.

公开(公告)号：US09390965B2

公开(公告)日：2016-07-12

申请号：US14135785

申请日：2013-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract translation: 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。

公开(公告)号：US20150179499A1

公开(公告)日：2015-06-25

申请号：US14135785

申请日：2013-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract translation: 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。