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    Semiconductor device with backside self-aligned power rail and methods of forming the same
    243.
    发明授权
    Semiconductor device with backside self-aligned power rail and methods of forming the same 有权

    公开(公告)号：US11444170B1

    公开(公告)日：2022-09-13

    申请号：US17199629

    申请日：2021-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

    Semiconductor devices with backside air gap dielectric
    244.
    发明授权
    Semiconductor devices with backside air gap dielectric 有权

    公开(公告)号：US11443987B2

    公开(公告)日：2022-09-13

    申请号：US16888217

    申请日：2020-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417

    Abstract: A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

    Gate patterning process for multi-gate devices
    246.
    发明授权
    Gate patterning process for multi-gate devices 有权

    公开(公告)号：US11387346B2

    公开(公告)日：2022-07-12

    申请号：US16858440

    申请日：2020-04-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

    Abstract: A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.

    Semiconductor device and method for making the same
    248.
    发明授权
    Semiconductor device and method for making the same 有权

    公开(公告)号：US11362191B2

    公开(公告)日：2022-06-14

    申请号：US16415136

    申请日：2019-05-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chi-Yi Chuang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

    Using a liner layer to enlarge process window for a contact via
    249.
    发明授权
    Using a liner layer to enlarge process window for a contact via 有权

    公开(公告)号：US11361986B2

    公开(公告)日：2022-06-14

    申请号：US16808902

    申请日：2020-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

    IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/417

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

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