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公开(公告)号：US12205651B2
公开(公告)日：2025-01-21
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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252.发明公开公开(公告)号：US20240048131A1
公开(公告)日：2024-02-08
申请号：US18350380
申请日：2023-07-11
Applicant: STMicroelectronics S.r.I.
Inventor： Marco Borghese
CPC classification number: H03K3/0315 , H02M3/157 , H03K7/08 , H02M1/0025
Abstract: A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.
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公开(公告)号：US20230384459A1
公开(公告)日：2023-11-30
申请号：US18312157
申请日：2023-05-04
Applicant: STMicroelectronics S.r.I.
Inventor： Gaetano Rivela
CPC classification number: G01S19/243 , G01S19/04
Abstract: In accordance with an embodiment, a system includes a phase-locked loop (PLL) configured to provide a first local oscillator (LO) signal and a voltage-controlled oscillator (VCO) signal; a first quadrature demodulator configured to downconvert global navigation satellite system signals to produce a first intermediate frequency (IF) signal; a first signal processing chain configured to pass the first IF signal; a second signal processing chain comprising a first frequency divider configured to produce a second LO signal based on the first LO signal, and a second quadrature demodulator configured to convert the first IF signal to a second IF signal using the second LO signal; and a third signal processing chain comprising a second frequency divider configured to produce a third LO signal based on the VCO signal, and a third quadrature demodulator configured to convert the first IF signal to a third IF signal using the third LO signal.
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公开(公告)号：US20230268830A1
公开(公告)日：2023-08-24
申请号：US18310824
申请日：2023-05-02
Applicant: STMicroelectronics S.r.I.
Inventor： Edoardo Botti
CPC classification number: H02M3/155 , H03F3/217 , H04R3/04 , H03F2200/03
Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.
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公开(公告)号：US20230170914A1
公开(公告)日：2023-06-01
申请号：US18054333
申请日：2022-11-10
Applicant: STMicroelectronics S.r.I.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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Patent Agency Ranking
公开(公告)号：US20230141001A1
公开(公告)日：2023-05-11
申请号：US17989877
申请日：2022-11-18
Applicant: STMicroelectronics S.r.I.
Inventor： Claudio Adragna , Francesco Ferrazza
CPC classification number: H02M3/33569 , H02M1/08
Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.
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公开(公告)号：US20230006546A1
公开(公告)日：2023-01-05
申请号：US17364147
申请日：2021-06-30
Applicant: STMicroelectronics S.r.I.
Inventor： Juri Giovannone , Valeria Bottarel , Stefano Corona
Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.
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公开(公告)号：US20220229887A1
公开(公告)日：2022-07-21
申请号：US17646981
申请日：2022-01-04
Applicant: STMicroelectronics S.r.I.
Inventor： Enrico Rosario Alessi , Simone Ferri , Fabio Passaniti
Abstract: To recognize an authorized user from an unauthorized user of a portable electronic apparatus, the portable electronic apparatus has a plurality of sensors and a user-recognition circuit. The sensors are each configured to generate a signal representative of a respective physical quantity associated with the use, by a user, of the portable electronic apparatus in an operating state. The user-recognition circuit is configured to receive a plurality of electrical signals from the plurality of sensors; determine a plurality of recognition parameters, each associated with a specific mode of use of the portable electronic apparatus by the user; determine a plurality of indicators of use, one for each recognition parameter, wherein each parameter indicates the probability that, at a time instant, the respective recognition parameter is associable with an unauthorized user; determine a probability of intrusion from the plurality of indicators of use; and compare the probability of intrusion with an intrusion threshold.
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公开(公告)号：US20220188610A1
公开(公告)日：2022-06-16
申请号：US17455770
申请日：2021-11-19
Inventor： Laurent Folliot , Mirko Falchetto , Pierre Demaj
Abstract: According to an aspect, a method is proposed for defining placements, in a volatile memory, of temporary scratch buffers used during an execution of an artificial neural network, the method comprising: determining an execution order of layers of the neural network, defining placements, in a heap memory zone of the volatile memory, of intermediate result buffers generated by each layer, according to the execution order of the layers, determining at least one free area of the heap memory zone over the execution of the layers, defining placements of temporary scratch buffers in the at least one free area of the heap memory zone according to the execution order of the layers.
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公开(公告)号：US20220013984A1
公开(公告)日：2022-01-13
申请号：US17360381
申请日：2021-06-28
Inventor： Romeo Letor , Vanni Poletto , Antoine Pavlin , Nadia Lecci , Alfio Russo
Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
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