公开(公告)号：US20200073430A1

公开(公告)日：2020-03-05

申请号：US16558717

申请日：2019-09-03

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti PANJA ,  Gautam Dey KANUNGO

IPC: G05F3/26

Abstract: A sub-bandgap reference voltage generator includes a reference current generator generating a reference current (proportional to absolute temperature), a voltage generator generating an input voltage (proportional to absolute temperature) from the reference current, and a differential amplifier. The differential amplifier is biased by the reference current and has an input receiving the input voltage and a resistor generating a voltage proportional to absolute temperature summed with the input voltage to produce a temperature insensitive output reference voltage. The reference current generator may generate the reference current as a function of a difference between bias voltages of first and second transistors. The voltage generator may generate the input voltage by applying the current proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, and tapping a node between given adjacent ones of the plurality of transistors.

公开(公告)号：US10566980B2

公开(公告)日：2020-02-18

申请号：US15924584

申请日：2018-03-19

Applicant: STMicroelectronics International N.V.

Inventor： Nitin Gupta ,  Jeet Narayan Tiwari

IPC: H03L7/07 ,  H03L7/099 ,  H03L7/095

Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

公开(公告)号：US10527672B2

公开(公告)日：2020-01-07

申请号：US15713168

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/28 ,  H03K19/20

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

公开(公告)号：US20190393779A1

公开(公告)日：2019-12-26

申请号：US16563069

申请日：2019-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA

IPC: H02M3/07 ,  H03K19/096 ,  G05F1/10

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US20190312575A1

公开(公告)日：2019-10-10

申请号：US16253410

申请日：2019-01-22

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K17/082 ,  H03K17/687 ,  G05F3/16 ,  H03K19/0185

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

公开(公告)号：US10418095B2

公开(公告)日：2019-09-17

申请号：US15978684

申请日：2018-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C7/04

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US10417364B2

公开(公告)日：2019-09-17

申请号：US15423292

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06F17/50 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

公开(公告)号：US20190279707A1

公开(公告)日：2019-09-12

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek PATHAK ,  Tanmoy ROY ,  Shishir KUMAR

IPC: G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20190273484A1

公开(公告)日：2019-09-05

申请号：US16296094

申请日：2019-03-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alok Kumar TRIPATHI ,  Amit VERMA ,  Anuj GROVER ,  Deepak Kumar BIHANI ,  Tanmoy ROY ,  Tanuj AGRAWAL

IPC: H03K3/3562 ,  G11C29/00

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

公开(公告)号：US20190266784A1

公开(公告)日：2019-08-29

申请号：US16280963

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06T15/08 ,  G06N3/08 ,  G06K9/00 ,  G06T7/62 ,  G06F9/38 ,  G06F16/901 ,  G06K9/62 ,  G06T7/11

Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.