公开(公告)号：US20050272105A1

公开(公告)日：2005-12-08

申请号：US10888530

申请日：2004-07-09

Applicant: Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

Inventor： Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

IPC: A61F13/15 ,  C12M1/34 ,  C12Q1/00 ,  G01N20060101 ,  G01N33/543 ,  G01N33/552 ,  G01N33/554 ,  G01N33/569

CPC classification number: C12Q1/00 ,  C07K9/00 ,  C07K14/32 ,  C07K17/00 ,  C12Q1/003 ,  G01N33/53 ,  G01N33/54353 ,  G01N33/5438 ,  G01N33/54393 ,  G01N33/552

Abstract: A real-time, portable peptide-containing potentiometric biosensor that can directly identify bacterial spores. Two peptides for specific recognition of B. subtilis and B. anthracis Sterne may be immobilized by a polysiloxane monolayer immobilization (PMI) technique. The sensors translate the biological recognition event into a potential change by detecting, for example, B. subtilis spores in a concentration range of 0.08-7.3×104 CFU/ml. The sensor exhibited highly selective recognition properties towards Bacillus subtilis spores over other kinds of spores. The selectivity coefficients of the sensors for other kinds of spores are in the range of 0-1.0×10−5. The biosensor system not only has the specificity to distinguish Bacillus subtilis spores in a mixture of B. subtilis and B. thuringiensis (thur.) Kurstaki spores, but also can discriminate between live and dead B. subtilis spores. Furthermore, the sensor can distinguish a Bacillus subtilis 1A700 from other B. subtilis strain. Assay time may be as low as about 5 minutes for a single test. Rapid identification of B. anthracis Sterne and B. anthracis ΔAmes was also provided.

Abstract translation: 一种可直接鉴定细菌孢子的实时便携式含肽电位生物传感器。 用于特异性识别枯草芽孢杆菌和炭疽芽孢杆菌的两种肽可以通过聚硅氧烷单层固定（PMI）技术来固定。 传感器通过检测例如浓度范围为0.08-7.3×10 4 CFU / ml的枯草芽孢杆菌孢子将生物识别事件转化为潜在的变化。 传感器表现出对枯草芽孢杆菌孢子与其他种类孢子的高选择性识别性能。 用于其他种类孢子的传感器的选择性系数在0-1.0×10 -5的范围内。 生物传感器系统不仅具有将枯草芽孢杆菌和苏云金芽孢杆菌（thur。）Kurstaki孢子的混合物中的枯草芽孢杆菌孢子区分开的特异性，而且可以区分活枯枯病芽孢杆菌孢子和活枯草芽孢杆菌孢子。 此外，传感器可以将枯草芽孢杆菌1A700与其他枯草芽孢杆菌菌株区分开来。 单次测试的测定时间可能低至约5分钟。 炭疽杆菌和炭疽杆菌的快速鉴定也提供了DeltaAmes。

公开(公告)号：US06960804B1

公开(公告)日：2005-11-01

申请号：US10633034

申请日：2003-10-10

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

IPC: H01L21/027 ,  H01L21/336 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/785 ,  H01L21/0276 ,  H01L29/42392 ,  H01L29/66795

Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

Abstract translation: 双半导体器件包括衬底，绝缘层，鳍和栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 翅片具有多个侧表面，顶表面和底表面。 栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。 用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

公开(公告)号：US06894355B1

公开(公告)日：2005-05-17

申请号：US10044493

申请日：2002-01-11

Applicant: Bin Yu ,  Olov Karlsson

Inventor： Bin Yu ,  Olov Karlsson

IPC: H01L21/28 ,  H01L27/01

CPC classification number: H01L21/28291

Abstract: A semiconductor device and method of manufacture. The semiconductor device having a silicide source and a silicide drain; a semiconductor body disposed between the source and the drain; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

Abstract translation: 半导体器件及其制造方法。 具有硅化物源和硅化物漏极的半导体器件; 设置在源极和漏极之间的半导体本体; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

公开(公告)号：US06787402B1

公开(公告)日：2004-09-07

申请号：US09845604

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21355

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A double-gate vertical MOSFET transistor is described along with an associated fabrication method. The MOSFET transistor is configured with separate gates on each side of a vertical source-drain channel that is capped by an insulation layer. The fabrication process generally comprises forming a silicon-insulator stack having a silicon fin (channel) capped with insulation. The opposing ends of the silicon-insulator stack being configured with areas capable of receiving source and drain contacts. The vertical surfaces of the silicon fin are insulated prior to the formation of gate electrodes adjacent the two opposing sides of the silicon-insulator stack. By way of example, the gate electrodes are formed by depositing a thick layer of conductive gate material over the substrate and then removing the adjoining upper portion, such as by polishing. Portions of each gate electrode are configured with areas capable of receiving a gate contact.

Abstract translation: 描述双栅垂直MOSFET晶体管以及相关的制造方法。 MOSFET晶体管在垂直源极 - 漏极沟道的每一侧配置有分隔的栅极，该栅极被绝缘层封住。 制造工艺通常包括形成具有用绝缘体封盖的硅片（通道）的硅 - 绝缘体堆叠。 硅 - 绝缘体堆叠的相对端被配置有能够接收源极和漏极接触的区域。 在形成邻近硅 - 绝缘体堆叠的两个相对侧的栅电极之前，硅片的垂直表面被绝缘。 作为示例，栅电极通过在衬底上沉积厚的导电栅极材料层，然后例如通过抛光去除邻接的上部而形成。 每个栅电极的部分配置有能够接收栅极接触的区域。

公开(公告)号：US06743689B1

公开(公告)日：2004-06-01

申请号：US10341427

申请日：2003-01-14

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

Abstract: Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

Abstract translation: 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

公开(公告)号：US06703277B1

公开(公告)日：2004-03-09

申请号：US10118437

申请日：2002-04-08

Applicant: Eric N. Paton ,  Bin Yu

Inventor： Eric N. Paton ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/31691 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/3115 ,  H01L21/31155 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor device and a process for fabricating the device, the process including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide. In another embodiment, the metal is implanted into the interfacial layer. A semiconductor device including such metal layer and implanted metal is also provided.

Abstract translation: 一种半导体器件和用于制造该器件的工艺，该工艺包括以下步骤：在硅衬底上沉积包含至少一种高K电介质材料的层，由此在硅衬底与硅衬底之间的界面处形成一定数量的二氧化硅 高K介电材料层; 在高K电介质材料层上沉积一层金属; 并且通过高K电介质材料层使金属扩散，由此金属将至少一部分二氧化硅还原为硅，并且金属被氧化以形成K值大于二氧化硅的电介质材料。 在另一个实施方案中，将金属注入界面层。 还提供了包括这种金属层和植入金属的半导体器件。

公开(公告)号：US06693333B1

公开(公告)日：2004-02-17

申请号：US09846912

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An integrated circuit can include gate structures designed to effect a work function of a transistor. A first set of gate structures can have a first work function and a second set of gate structures can have a second work function. The gate structures include metal layers to affect changes in the work function. The work function can affect the threshold voltage associated with the transistors. The transistor can be built on a silicon-on-insulator substrate.

Abstract translation: 集成电路可以包括设计用于实现晶体管的功函数的栅极结构。 第一组门结构可以具有第一功函数，第二组门结构可以具有第二功函数。 栅极结构包括影响功函数变化的金属层。 工作功能可以影响与晶体管相关的阈值电压。 晶体管可以建立在绝缘体上硅衬底上。

公开(公告)号：US06646307B1

公开(公告)日：2003-11-11

申请号：US10081362

申请日：2002-02-21

Applicant: Bin Yu ,  Eric N. Paton

Inventor： Bin Yu ,  Eric N. Paton

IPC: H01L2701

CPC classification number: H01L29/6675 ,  H01L29/78618 ,  H01L29/78648

Abstract: A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.

Abstract translation: 双栅极MOSFET。 MOSFET包括设置在底栅电极上的底栅电极和底栅电介质。 半导体本体区域设置在底栅电介质和底栅电极之上，并且设置在源极和漏极之间。 顶栅电极设置在身体上。 顶栅电介质分离顶栅电极和主体，顶栅电极和底栅电极在主体内限定通道并置于源极和漏极之间。 底栅电介质或顶栅电介质中的至少一个由高K材料形成。 还公开了一种形成双栅极MOSFET的方法，其中用于形成本体的半导体膜使用半导体衬底作为晶种再结晶。

公开(公告)号：US06630712B2

公开(公告)日：2003-10-07

申请号：US09372705

申请日：1999-08-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K dielectric spacers can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs). The T-shaped conductor forms dynamic source/drain extensions.

Abstract translation: 公开了一种制造具有对截止状态漏电流和短沟道效应的敏感性较小的晶体管的集成电路的方法。 晶体管包括高K栅极电介质隔离物和T形栅极导体。 高K电介质隔离物可以是五氧化钽或二氧化钛。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 T形导体形成动态源/漏扩展。

公开(公告)号：US06630385B1

公开(公告)日：2003-10-07

申请号：US09844773

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less. The method includes a deep source/drain implant and anneal, followed by an angled deep halo implant and a second anneal at a lower temperature. An amorphization implant is then made, followed by a second angled halo implant, formation of source/drain extensions and a third anneal at a temperature less than the second anneal.

Abstract translation: 一种改进深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法。 该方法涉及在不同温度下退火的双光晕植入物，以改善约50nm或更小的MOSFET的阈值电压滚降特性。 该方法包括深源/漏植入和退火，随后是斜角深晕植入和在较低温度下的第二退火。 然后制造非晶化植入物，随后是第二成角度的晕轮植入物，在低于第二次退火的温度下形成源极/漏极延伸部分和进行第三次退火。