公开(公告)号：US09949108B2

公开(公告)日：2018-04-17

申请号：US15472907

申请日：2017-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Nicolas Cordier ,  Vinko Kunc ,  Maksimiljan Stiglic

IPC: H04W8/00 ,  H04W40/24 ,  H04W76/02 ,  H04B5/00 ,  H04W48/10 ,  H04W4/00

CPC classification number: H04W8/005 ,  H04B5/0025 ,  H04W4/80 ,  H04W48/10

Abstract: According to an embodiment, a method can be performed by a first active near-field communication (NFC) device. The method includes assuming a field detection mode, generating an advertisement pulse, and checking whether a predefined condition is fulfilled. If the checking determines that the predefined condition is fulfilled, the method includes assuming an active mode and communicating with an adjacent active NFC device, and, if the checking does not determine that the predefined condition is fulfilled, the method includes staying in the field detection mode and generating another advertisement pulse.

公开(公告)号：US09941885B2

公开(公告)日：2018-04-10

申请号：US15257693

申请日：2016-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Singh

IPC: H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356104 ,  H03K19/0013

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

公开(公告)号：US09941875B2

公开(公告)日：2018-04-10

申请号：US15615178

申请日：2017-06-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K19/20 ,  H03K5/19

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US20180096256A1

公开(公告)日：2018-04-05

申请号：US15833457

申请日：2017-12-06

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Arun Kumar ,  Ghanapriya Singh ,  Kashif R. J. Meer ,  Indra Narayan Kar ,  Rajendar Bahl

IPC: G06N7/00 ,  G06F17/30

CPC classification number: G06N7/005 ,  G06F16/2455 ,  H04M1/72569 ,  H04W4/02 ,  H04W4/38

Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.

公开(公告)号：US20180090060A1

公开(公告)日：2018-03-29

申请号：US15809007

申请日：2017-11-10

Applicant: STMicroelectronics International N.V.

Inventor： Jerome Nebon ,  Jean-Marie Permezel

IPC: G09G3/325 ,  G09G3/3266 ,  G09G3/3225 ,  G09G3/3275

CPC classification number: G09G3/325 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275 ,  G09G2300/0413 ,  G09G2300/08 ,  G09G2300/0866 ,  G09G2320/041

Abstract: A device includes a matrix of active pixels, with each active pixel having an OLED diode having a cathode to receive a cathode voltage, and a control circuit coupled to an anode of the OLED diode. The device also includes at least one dummy pixel having a dummy OLED diode having a cathode to receive the cathode voltage, and an anode, and a dummy control circuit coupled to the anode of the OLED diode and having a power supply terminal. The dummy OLED diode and the dummy control circuit are substantially similar to the OLED diode and the control circuit. First regulation circuitry is configured to deliver a reference current to the power supply terminal to thereby generate a voltage, and second regulation circuitry is configured to regulate the cathode voltage so as to maintain the voltage at the power supply terminal at a given level.

公开(公告)号：US20180083603A1

公开(公告)日：2018-03-22

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/356 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/02335 ,  H03K3/35625 ,  H03K19/0002

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US09921405B2

公开(公告)日：2018-03-20

申请号：US15401681

申请日：2017-01-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Benedetto Vigna ,  Marco Ferrera ,  Sonia Costantini ,  Marco Salina

IPC: G02B26/08 ,  H04N9/31 ,  H02N1/00 ,  B81B3/00 ,  B81C1/00 ,  G02B27/10

CPC classification number: G02B26/0841 ,  B81B3/0045 ,  B81B2201/042 ,  B81B2203/0154 ,  B81C1/00198 ,  G02B27/1006 ,  H02N1/002 ,  H02N1/006 ,  H04N9/3129 ,  H04N9/3135 ,  Y10T29/49002

Abstract: An electrostatically actuated oscillating structure includes a first stator subregion, a second stator subregion, a first rotor subregion and a second rotor subregion. Torsional elastic elements mounted to the first and second rotor subregions define an axis of rotation. A mobile element is coupled to the torsional elastic elements. The stator subregions are electrostatically coupled to respective regions of actuation on the mobile element. The stator subregions exhibit an element of structural asymmetry such that the electrostatic coupling surface between the first stator subregion and the first actuation region differs from the electrostatic coupling surface between the second stator subregion and the second actuation region.

公开(公告)号：US09921058B2

公开(公告)日：2018-03-20

申请号：US14281273

申请日：2014-05-19

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Kumar Sinha ,  Nishant Omar

IPC: G01B21/00 ,  G01C21/16 ,  G06K9/00 ,  H05B37/02

CPC classification number: G01B21/00 ,  G01C21/16 ,  G06K9/00348 ,  H05B37/029

Abstract: Methods and systems for dynamic tracking of on-stage objects using microelectromechanical systems (MEMS) presented herein do not require illumination to track a randomly moving object and are easily configurable for various stage sizes and for stages movable relative to the ground. In some instances, a tracking method includes determining an initial state of an MEMS motion tracker carried on a dynamic object, such as a performer. Acceleration and orientation information gathered by the motion tracker is monitored. A change of state in response to the monitored acceleration and orientation information is then determined. An instant state is calculated using the change of state and the initial state. Actuation signals based on the calculated instant state are generated for actuating a gimbal. The gimbal faces a device supported thereby toward the dynamic object.

公开(公告)号：US09891279B2

公开(公告)日：2018-02-13

申请号：US13919884

申请日：2013-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Ajay Kumar Dimri

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31726 ,  G01R31/318552

Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.

公开(公告)号：US20180031631A1

公开(公告)日：2018-02-01

申请号：US15223061

申请日：2016-07-29

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Tripti Gupta

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318544 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318572

Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.