公开(公告)号：US20250022492A1

公开(公告)日：2025-01-16

申请号：US18766414

申请日：2024-07-08

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G11C5/14

Abstract: A method includes determining that a power event involving a memory sub-system has occurred. The method further including in response to the determination that the power event has occurred, generating signaling indicative of performance of an operation to provide power to a plurality of memory components of the memory sub-system, where the signaling indicative of performance includes a power control signal is applied to a first memory component at a first time, and is applied to a second memory component at a second time that is subsequent to the first memory component entering a steady state.

公开(公告)号：US20250021386A1

公开(公告)日：2025-01-16

申请号：US18900059

申请日：2024-09-27

Applicant: Micron Technology, Inc.

Inventor： Carla L. Christensen ,  Reshmi Basu

IPC: G06F9/50 ,  G06F3/06 ,  G06F11/30 ,  G06F11/34 ,  H04L67/10 ,  H04L67/50

Abstract: Methods, systems, and apparatuses related to management of a computing device usage profile are described. The usage profile can be a usage profile of a computing device. Characteristics of workloads executed by a computing device can be monitored to determine whether performance of the computing device can be optimized by execution of an updated usage profile. Responsive to a determination that the performance of the computing device can be improved by execution of an updated usage profile, the updated usage profile can be received by the computing device and executed thereon.

公开(公告)号：US20250021262A1

公开(公告)日：2025-01-16

申请号：US18904757

申请日：2024-10-02

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

公开(公告)号：US20250021253A1

公开(公告)日：2025-01-16

申请号：US18770896

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.

公开(公告)号：US12199650B2

公开(公告)日：2025-01-14

申请号：US18179249

申请日：2023-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H04B1/04 ,  G06N3/044 ,  H03F3/20

Abstract: Examples described herein include methods, devices, and systems which may compensate input data for nonlinear power amplifier noise to generate compensated input data. In compensating the noise, during an uplink transmission time interval (TTI), a switch path is activated to provide amplified input data to a receiver stage including a recurrent neural network (RNN). The RNN may calculate an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate filter coefficient data associated with the power amplifier noise. The feedback signal is provided, after processing through the receiver, to the RNN. During an uplink TTI, the amplified input data may also be transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path may be deactivated and the receiver stage may receive an additional RF wireless transmission to be processed in the receiver stage.

公开(公告)号：US12198776B2

公开(公告)日：2025-01-14

申请号：US17648393

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44 ,  H03K19/173

Abstract: Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.

公开(公告)号：US12197754B2

公开(公告)日：2025-01-14

申请号：US18337873

申请日：2023-06-20

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. The host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. The host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. The host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.

公开(公告)号：US12197742B2

公开(公告)日：2025-01-14

申请号：US17860701

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: Embodiments disclosed can include determining, for each memory cell connected to each wordline, a respective value of a metric that reflects a sensitivity of a threshold voltage associated with the memory cell to a change in a threshold voltage of an adjacent cell and determining, for each wordline, based on the determined sensitivity for each memory cell, a respective aggregate measure of adjacent cell dependence. They can further include comparing the determined aggregate measure of adjacent cell dependence to a threshold dependence value. They can also include identifying a first wordline group having wordlines with high adjacent cell dependence and a second wordline group having wordlines with low adjacent cell dependence and storing a record referencing the wordlines of the second wordline group, the record indicating a corresponding location on the die of the memory device.

公开(公告)号：US12197739B2

公开(公告)日：2025-01-14

申请号：US17888080

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/32

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

公开(公告)号：US20250016440A1

公开(公告)日：2025-01-09

申请号：US18897166

申请日：2024-09-26

Applicant: Micron Technology, Inc.

Inventor： Marta Egorova

IPC: H04N23/60 ,  H04N23/50 ,  H04N23/90

Abstract: Methods and devices related to selecting image sensors are described. In an example, a method can include receiving, at a processing resource of a computing device, first signaling indicative of image data from a plurality of image sensors that are located under a surface of a display of the computing device; receiving, at the processing resource of the computing device, second signaling indicative of display data indicating a first portion of the display is active when the computing device is running an application, determining, at the processing resource, that a first image sensor of the plurality of sensors is closest to the first portion of the display, and selecting the first image sensor of the plurality of sensors closest to the first portion of the display for generating image data for the application.