Abstract:
The present disclosure relates to an electronic analog-to-digital conversion device (100) which comprises: an analog-to-digital conversion block (101) having a first input (1) for receiving a voltage signal (Vout) to be converted on the basis of a reference voltage signal (VREF) provided to a second input (2) of the same analog-to-digital conversion block (101);—an input block (102) having an input terminal (3) and an output terminal (4) connected to the first input (1) of the analog-to-digital conversion block (101). The input block (102) is arranged for processing an input voltage signal (Vin) applied to the input terminal (3) to generate the voltage signal (Vout) at the output terminal (4). The input block (102) comprises:—a first resistive network (103) operatively connected to both the input terminal (3) and the output terminal (4);—a second resistive network (104) connected between the output terminal (4) and a reference potential (GND). The input block (102) is characterized by comprising an active network (105) connected between an output node (5) of the first resistive network (103) and the output terminal (4). The active network (105) has a first input terminal (6) directly connected to the second input (2) of the analog-to-digital conversion block (101) for receiving the same reference voltage signal (VREF) provided to the second input (2) so that the input voltage signal (Vin) is processed by the input block (102) on the basis of such reference voltage signal (VREF).
Abstract:
A signal is detected and an unwanted jamming signal is removed from the detected signal. Respective first, second and third correlations between a received signal and signals at first, second and third frequencies are determined over a plurality of taps. The second frequency is higher than the first frequency and lower than the third frequency, and is equally spaced from the first and third frequencies. The second frequency is adapted to a frequency of the received signal such that peaks in the first and third correlations after corresponding adaptation of the first and third frequencies have substantially equal magnitudes. A difference is determined between non-peak magnitudes of the first and third correlations; and at least one of the correlations is compensated for the effects of the jamming signal, based on said difference.
Abstract:
A sequential estimation method for real-time positioning or navigation systems is performed by, at each iteration: propagating a first state estimate into a state prediction, and then forming a second state estimate, by updating the state prediction using state measurements. The first state estimate is valid at a first time and comprises estimated values of a plurality of state parameters, the plurality of state parameters including at least one state parameter referring to a time earlier than the first time. The second state estimate is valid at a second time and comprises estimated values of said plurality of state parameters, the plurality of state parameters including at least one state parameter referring to a time earlier than the second time. The state measurements comprise measurements relating to state parameters at the second time and measurements relating to state parameters at the time earlier than the second time.
Abstract:
A resource management unit for a mobile telephone terminal, with the terminal comprising radio transmission/reception means for transmitting and receiving radio frequency signals corresponding to bursts of symbols during allocated time slots, and a device able to operate in a first mode and in a second mode, said device interfering less with the transmission/reception of radio frequency signals when it is in the first mode than when it is in the second mode. The resource management unit is able to cause the device to change from one of the first and second modes to the other of the first and second modes during the same time slot.
Abstract:
According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N−1 SAR cycles, the Nth SAR cycle is performed by setting a Nth tentative analog signal corresponding to a provisional digital code and comparing the Nth tentative analog signal with the sampled analog signal to obtain a Nth comparison result. The (N+1)th SAR cycle is performed by setting a (N+1)th tentative analog signal based on the Nth comparison result, comparing the (N+1)th tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)th comparison result to obtain the output digital code. The Nth and (N+1)th SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.
Abstract:
Systems and method provide for cell reconfirmation methods for a multi-Radio Access Technology (RAT) capable User Equipment (UE). A method for performing a cell reconfirmation method by a multi-Radio Access Technology (RAT) capable User Equipment (UE), the method includes: performing, by the UE, cell reconfirmation using information derived from a Normal Burst (NB) of a transmitted Global System for Mobile communication (GSM) radio signal, wherein the cell reconfirmation verifies an identity of a GSM cell associated with the transmitted GSM radio signal. The method can further include: operating the multi-RAT capable UE in a serving cell of a first RAT; and selecting the cell reconfirmation method to reconfirm a Global System for Mobile (GSM) communication neighbor cell located in a second RAT which is a GSM RAT, wherein a first cell reconfirmation method uses a received Normal Burst (NB) and a second cell reconfirmation method uses a received Synchronization Burst (SB).
Abstract:
The present invention relates to method and apparatus for uplink data transmission, a user equipment, a computer program and a storage medium. The method comprises: acquiring a data error rate of data blocks transmitted on an uplink of a UE; constructing a new data block, wherein a size of the new data block is smaller than the size of the transmitted data block currently, if the block error rate is greater than a threshold; and transmitting the new data block on the uplink of the UE according to a first power currently allocated to the UE. The present invention can enhance the performance of uplink data transmission.
Abstract:
A UE side Broadcast/Multicast Control (BMC) protocol layer determines those Cell Broadcast Service (CBS) messages (and their repetitions) which the UE shall read or ignore in a succeeding CBS schedule period, based on the CBS Schedule Message contents (Message Description Type and New Message Bitmap) received in a current CBS schedule period, the CBS messages already stored in the BMC, and the CBS messages to be received. In this manner, the UE may ignore CBS messages it has already received, without knowledge of the CBS message serial numbers, and thus conserve resources such as battery power.
Abstract:
The invention concerns a device for providing a spread frequency clock signal, comprising: —an input (51) to receive a first clock signal having a first frequency; —a programmable clock divider (52) to generate the spread frequency clock signal from the first clock signal; —a first Feedback Shift Register (21), FSR, comprising at least one stage, the FSR being adapted to generate any of an odd number M of different values, the FSR being adapted to pseudo-randomly generate a first sequence of first output values, each corresponding to one of said M different values, and to provide a first output value, according to the sequence, during each clock cycle of the spread frequency clock signal; —a control unit (22) adapted to select a division factor of the programmable clock divider based on the first output value of the FSR during each clock cycle of the spread frequency clock signal; —an output (53) for providing the spread frequency clock signal.
Abstract:
A multiphase buck converter (10) is disclosed, comprising: —a first buck converter branch (SD1, L1) comprising a first core section (COR1), a first power section (PWR1) having a first output node (LX1), a first coil (11) having a first end connected to the first output node (LX1), the first power section (PWR1) being adapted to be controlled by the first core section (COR1) for providing to the coil (L1) a coil current (I1), the first core section (COR1) and the first power section (PWR1) being integrated in a chip (IC); -a second buck converter branch (SD2, L2) comprising a second core section (COR2), a second power section (PWR2) having a second output node (LX2), a second coil (L2) having a first end connected to the second output node (LX2), the second power section (PWR2) being adapted to be controlled by the second core section (COR2) for providing to the second coil (L2) a second coil current (I2), the second core section (COR2) and the second power section (PWR2) being integrated in said chip (IC); -a feedback loop adapted to balance said coil currents (I1,I2). The feedback loop comprises a control block (C_B) that, in order to balance said coil currents, is adapted to compare a first average voltage at the first output node (LX1) with a second average voltage at the second output node (LX2) and control the first (SD1, L1) and second branch (SD2, L2) in order to make said first and second average voltages equal to each other. The control block (C_B) is integrated in said chip (IC) and has a first input directly connected to said first output node (LX1) and a second input directly connected to said second output node (LX2). The control block (C_B) is adapted to directly obtain said first and second average voltages from the instantaneous voltages of the first (LX1) and second (LX2) output nodes.