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公开(公告)号：US20220416743A1
公开(公告)日：2022-12-29
申请号：US17839335
申请日：2022-06-13
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto MODAFFARI , Paolo PESENTI , Mario MAIORE , Tiziano CHIARILLO
Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
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公开(公告)号：US20220416657A1
公开(公告)日：2022-12-29
申请号：US17841182
申请日：2022-06-15
Applicant: STMicroelectronics S.r.l.
Inventor： Ivan Floriani , Elena Brigo
Abstract: In an embodiment a control device includes a first input configured to receive a measurement signal representative of an output voltage of a switching circuit of a voltage regulator, a state determination block coupled to the first input and configured to generate a signal of actual operating condition of the voltage regulator and a driving signals generation module configured to generate at least one switching command signal for the switching circuit from an error signal representative of a difference between the output voltage and a nominal voltage, wherein the driving signals generation module includes an error-compensation circuit having a transfer function and configured to generate a control signal from the error signal and the actual operating condition signal, the control signal being a function of the actual operating condition.
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公开(公告)号：US20220416656A1
公开(公告)日：2022-12-29
申请号：US17807466
申请日：2022-06-17
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Borghese , Mattia Carrera
Abstract: In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.
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264.发明申请公开(公告)号：US20220415705A1
公开(公告)日：2022-12-29
申请号：US17848050
申请日：2022-06-23
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Daria DORIA
IPC: H01L21/768 , H01L21/283 , H01L23/532
Abstract: An integrated electronic device including: a main body delimited by a front surface; a top conductive region extending within the main body, starting from the front surface; a first dielectric region extending on the front surface; and a barrier structure, arranged on the first dielectric region. A first aperture extends through the barrier structure and the first dielectric region; the first aperture is delimited at bottom by the top conductive region. The integrated electronic device further includes a contact structure including at least a first conductive region extending within the first aperture, in direct contact with the top conductive region and the barrier structure.
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公开(公告)号：US20220415703A1
公开(公告)日：2022-12-29
申请号：US17357826
申请日：2021-06-24
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Mikel AZPEITIA URQUIA , Lorenzo TENTORI
Abstract: The present disclosure is directed to at least one embodiment of a die including a sidewall having a uniform surface and an irregular surface. The uniform surface may be a scalloped surface and scallops of the scalloped surface are substantially the same size and shape relative to each other. The irregular surface has a more irregular texture as compared to the uniform surface. The irregular surface may include a plurality of randomly spaced high points and a plurality of randomly spaced low points that are between adjacent ones of the high points. In a method of manufacturing the die, a cavity is pre-formed in a substrate and a multilayer structure is formed on the substrate. The multilayer structure includes an active area that is aligned with and overlies the cavity. After the multilayer structure is formed, at least one recess is formed extending into the multilayer structure to the cavity. Forming the recess forms a die structure suspended above the cavity and an extension extending from the die structure to a suspension structure surrounding the die structure. The die structure is released from the die suspension structure by breaking the extension.
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Patent Agency Ranking
公开(公告)号：US20220415655A1
公开(公告)日：2022-12-29
申请号：US17847679
申请日：2022-06-23
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo BADALA' , Anna BASSI , Massimo BOSCAGLIA , Valentina SCUDERI , Giovanni FRANCO
IPC: H01L21/04 , H01L29/16 , H01L29/872 , H01L29/78
Abstract: A metal layer is deposited on a wafer that has silicon carbide, wherein the metal layer forms a contact face. A laser annealing is performed at the contact face using a laser beam application that causes the metal layer to react with the wafer and form a silicide layer. The laser beam has a footprint having a size. To laser anneal the contact face, a first portion of the contact face is irradiated, the footprint of the laser beam is moved by a step smaller than the size of the footprint, and a second portion of the contact face is irradiated, thereby causing the first portion and the second portion of the contact face to overlap.
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公开(公告)号：US11537153B2
公开(公告)日：2022-12-27
申请号：US16459169
申请日：2019-07-01
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Orazio Cavallaro , Germano Nicollini , Giuseppe Palmisano
Abstract: A voltage reference circuit includes a first circuit block configured to generate a proportional to absolute temperature current, the first circuit block comprising a current mirror amplifier, a second circuit block coupled to the first circuit block and configured to generated a complimentary to absolute temperature current, and a third circuit block coupled to both the first circuit block and the second circuit block. The second circuit block includes a multi-stage common-source amplifier. The third circuit block is configured to combine the proportional to absolute temperature current and the complimentary to absolute temperature current to generate a reference voltage at an output of the voltage reference circuit.
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公开(公告)号：US20220404150A1
公开(公告)日：2022-12-22
申请号：US17821724
申请日：2022-08-23
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Alessandro TOCCHIO , Luca Giuseppe FALORNI , Claudia COMI , Valentina ZEGA
IPC: G01C19/5747 , G01C19/574 , G01C19/5769
Abstract: A frequency modulation MEMS triaxial gyroscope, having two mobile masses; a first and a second driving body coupled to the mobile masses through elastic elements rigid in a first direction and compliant in a second direction transverse to the first direction; and a third and a fourth driving body coupled to the mobile masses through elastic elements rigid in the second direction and compliant in the first direction. A first and a second driving element are coupled to the first and second driving bodies for causing the mobile masses to translate in the first direction in phase opposition. A third and a fourth driving element are coupled to the third and fourth driving bodies for causing the mobile masses to translate in the second direction and in phase opposition. An out-of-plane driving element is coupled to the first and second mobile masses for causing a translation in a third direction, in phase opposition. Movement-sensing electrodes generate frequency signals as a function of external angular velocities.
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公开(公告)号：US11526190B2
公开(公告)日：2022-12-13
申请号：US16868799
申请日：2020-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
IPC: G05F3/26
Abstract: An apparatus includes a current mirror coupled to an output of an amplifier through control switches, a plurality of capacitors, each of which is coupled to a common node of a leg of the current mirror and a corresponding control switch, a first dipole coupled to a first input of an amplifier, a second dipole coupled to a second input of the amplifier, a third dipole coupled to an output of the apparatus configured to generate the bandgap reference voltage, and groups of switches coupled between the current mirror and the dipoles.
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公开(公告)号：US20220393579A1
公开(公告)日：2022-12-08
申请号：US17732281
申请日：2022-04-28
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pulvirenti
IPC: H02M3/07
Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
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