公开(公告)号：US10418365B2

公开(公告)日：2019-09-17

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US10403548B2

公开(公告)日：2019-09-03

申请号：US15811965

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hong Yu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: The disclosure relates to integrated circuit (IC) structures with a single diffusion break (SDB) and end isolation regions, and methods of forming the same after forming a metal gate. A structure may include: a plurality of fins positioned on a substrate; a plurality of metal gates each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of metal gates; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins; an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of metal gates; and an insulator cap positioned on an upper surface of at least a portion of one of the plurality of metal gates.

公开(公告)号：US10332897B2

公开(公告)日：2019-06-25

申请号：US16133176

申请日：2018-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L27/11 ,  H01L29/66 ,  H01L27/02

Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.

公开(公告)号：US20190148242A1

公开(公告)日：2019-05-16

申请号：US15811965

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Hong Yu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0649

Abstract: The disclosure relates to integrated circuit (IC) structures with a single diffusion break (SDB) and end isolation regions, and methods of forming the same after forming a metal gate. A structure may include: a plurality of fins positioned on a substrate; a plurality of metal gates each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of metal gates; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins; an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of metal gates; and an insulator cap positioned on an upper surface of at least a portion of one of the plurality of metal gates.

公开(公告)号：US20190148240A1

公开(公告)日：2019-05-16

申请号：US16243863

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

公开(公告)号：US10290712B1

公开(公告)日：2019-05-14

申请号：US15797606

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

公开(公告)号：US20190123162A1

公开(公告)日：2019-04-25

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

公开(公告)号：US10269983B2

公开(公告)日：2019-04-23

申请号：US15590409

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/41

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

公开(公告)号：US20190108873A1

公开(公告)日：2019-04-11

申请号：US15729067

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11 ,  H01L29/78 ,  G11C11/412 ,  H01L21/8238

Abstract: Integrated circuits including a static random access memory (SRAM) cell, methods of operating the same, and methods of fabricating the same are provided herein. In an embodiment, an integrated circuit includes the SRAM cell. The SRAM cell includes a first pass-gate transistor and a second pass-gate transistor. The SRAM cell further includes a first word line and a second word line. The first word line and the second word line are electrically independent of each other. The first pass-gate transistor and/or the second pass-gate transistor include a first gate in electrical communication with the first word line and a second gate in electrical communication with the second word line with the first gate and the second gate included in the same pass-gate transistor.