公开(公告)号：US20210159318A1

公开(公告)日：2021-05-27

申请号：US17100559

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck JULIEN ,  Stephan NIEL ,  Leo GAVE

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/51

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US20210151559A1

公开(公告)日：2021-05-20

申请号：US17095230

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/8248 ,  H01L29/66 ,  H01L29/808

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US20210111133A1

公开(公告)日：2021-04-15

申请号：US17130683

申请日：2020-12-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier

IPC: H01L23/00 ,  H01L23/48 ,  G06F21/87 ,  H01L23/522

Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a backside of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the backside of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the backside, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.

公开(公告)号：US20210074749A1

公开(公告)日：2021-03-11

申请号：US17011900

申请日：2020-09-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thomas DALLEAU

IPC: H01L27/146 ,  H04N5/3745

Abstract: A pixel includes a photodiode and first and second transistors, the first and second transistors being coupled in series. One of the first and second transistors is a P channel transistor and the other is an N channel transistor. An electronic device may include one or more of the pixels.

公开(公告)号：US20210057426A1

公开(公告)日：2021-02-25

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto PIAZZA ,  Sebastien LAGRASTA ,  Raul Andres BIANCHI ,  Simon JEANNOT

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20210050224A1

公开(公告)日：2021-02-18

申请号：US16990556

申请日：2020-08-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Joel SCHMITT ,  Bilel SAIDI ,  Sylvain JOBLOT

IPC: H01L21/3205 ,  H01L23/528 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3215

Abstract: An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.

公开(公告)号：US10924700B2

公开(公告)日：2021-02-16

申请号：US16599875

申请日：2019-10-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Malinge

IPC: H04N5/3745 ,  H04N5/235 ,  G09G5/42

Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.

公开(公告)号：US20210041727A1

公开(公告)日：2021-02-11

申请号：US17083525

申请日：2020-10-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Frédéric Boeuf

IPC: G02F1/025 ,  H01L29/66

Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.

公开(公告)号：US10903259B2

公开(公告)日：2021-01-26

申请号：US16451918

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Axel Crocherie

IPC: H01L27/146

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.

公开(公告)号：US10892291B2

公开(公告)日：2021-01-12

申请号：US16285306

申请日：2019-02-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sonarith Chhun ,  Gregory Imbert

IPC: H01L27/146 ,  H01L21/84 ,  H01L23/48 ,  H01L21/762 ,  H01L27/06 ,  H01L27/12 ,  H01L21/3065 ,  H01L23/00 ,  H01L23/552 ,  H01L29/94

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.