公开(公告)号：US20210111133A1

公开(公告)日：2021-04-15

申请号：US17130683

申请日：2020-12-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier

IPC: H01L23/00 ,  H01L23/48 ,  G06F21/87 ,  H01L23/522

Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a backside of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the backside of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the backside, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.

公开(公告)号：US12087708B2

公开(公告)日：2024-09-10

申请号：US17451718

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoit Froment

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/64 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565 ,  H01L23/293

Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

公开(公告)号：US10903174B2

公开(公告)日：2021-01-26

申请号：US16043289

申请日：2018-07-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier

IPC: H01L23/00 ,  H01L23/48 ,  G06F21/87 ,  H01L23/522

Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.

公开(公告)号：US11387195B2

公开(公告)日：2022-07-12

申请号：US17130683

申请日：2020-12-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier

IPC: H01L23/00 ,  H01L23/48 ,  G06F21/87 ,  H01L23/522

Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a backside of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the backside of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the backside, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.

公开(公告)号：US20190035747A1

公开(公告)日：2019-01-31

申请号：US16043289

申请日：2018-07-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier

IPC: H01L23/00 ,  G06F21/87 ,  H01L23/522

Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.

公开(公告)号：US11183468B2

公开(公告)日：2021-11-23

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/64 ,  H01L23/58 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US10754618B2

公开(公告)日：2020-08-25

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  H01L21/768 ,  G06F21/70 ,  H04L9/08

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US20190034168A1

公开(公告)日：2019-01-31

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  G06F21/70 ,  H01L21/768

CPC classification number: G06F7/588 ,  G06F21/70 ,  H01L21/76829 ,  H04L9/0866

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.