公开(公告)号：US10903259B2

公开(公告)日：2021-01-26

申请号：US16451918

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Axel Crocherie

IPC: H01L27/146

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.

公开(公告)号：US20150118805A1

公开(公告)日：2015-04-30

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US11949035B2

公开(公告)日：2024-04-02

申请号：US17546503

申请日：2021-12-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Denis Rideau ,  Dominique Golanski ,  Alexandre Lopez ,  Gabriel Mugny

IPC: H01L31/107 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L31/186

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

公开(公告)号：US20200013820A1

公开(公告)日：2020-01-09

申请号：US16451918

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Axel Crocherie

IPC: H01L27/146

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.

公开(公告)号：US09356090B2

公开(公告)日：2016-05-31

申请号：US14640705

申请日：2015-03-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Fiori ,  Sebastien Gallois-Garreignot ,  Denis Rideau ,  Clement Tavernier

IPC: H01L29/04 ,  H01L29/78

CPC classification number: H01L29/045 ,  H01L23/522 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.

Abstract translation: 衬底包括沿结晶面（100）取向并被绝缘区域限制的有源区。 MOS晶体管包括沿着<110>型晶体方向纵向取向的通道。 由金属形成并形成为T形状的基本图案是电惰性的，并且位于与通道的横向端部相邻的绝缘区域的区域上。 T形基本图案的水平分支基本上平行于通道的纵向定向。

公开(公告)号：US11581449B2

公开(公告)日：2023-02-14

申请号：US16703689

申请日：2019-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Younes Benhammou ,  Dominique Golanski ,  Denis Rideau

IPC: H01L31/107 ,  H01L31/028 ,  H01L31/0745 ,  H01L31/18

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

公开(公告)号：US20200013812A1

公开(公告)日：2020-01-09

申请号：US16451856

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel Crocherie ,  Denis Rideau

IPC: H01L27/146 ,  H04N5/341

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. The pixels include a first pixel of a first type formed inside and on top of a first portion of the semiconductor layer and a second pixel of a second type formed inside and on top of a second portion of the semiconductor layer. The first pixel has a first thickness that defines a vertical cavity resonating at a first wavelength and the second pixel has a second thickness different from the first thickness. The second thickness defines a vertical cavity resonating at a second wavelength different than the first wavelength.

公开(公告)号：US11049892B2

公开(公告)日：2021-06-29

申请号：US16451856

申请日：2019-06-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel Crocherie ,  Denis Rideau

IPC: H01L27/146 ,  H04N5/341

Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. The pixels include a first pixel of a first type formed inside and on top of a first portion of the semiconductor layer and a second pixel of a second type formed inside and on top of a second portion of the semiconductor layer. The first pixel has a first thickness that defines a vertical cavity resonating at a first wavelength and the second pixel has a second thickness different from the first thickness. The second thickness defines a vertical cavity resonating at a second wavelength different than the first wavelength.

公开(公告)号：US09318372B2

公开(公告)日：2016-04-19

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

公开(公告)号：US20150311277A1

公开(公告)日：2015-10-29

申请号：US14640705

申请日：2015-03-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Fiori ,  Sebastien Gallois-Garreignot ,  Denis Rideau ,  Clement Tavernier

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/045 ,  H01L23/522 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.

Abstract translation: 衬底包括沿结晶面（100）取向并被绝缘区域限制的有源区。 MOS晶体管包括沿着<110>型晶体方向纵向取向的通道。 由金属形成并形成为T形状的基本图案是电惰性的，并且位于与通道的横向端部相邻的绝缘区域的区域上。 T形基本图案的水平分支基本上平行于通道的纵向定向。