公开(公告)号：US11646069B2

公开(公告)日：2023-05-09

申请号：US17460348

申请日：2021-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: H10B61/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/02 ,  H01L43/12

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

公开(公告)号：US20230135098A1

公开(公告)日：2023-05-04

申请号：US17541280

申请日：2021-12-03

Applicant: United Microelectronics Corp.

Inventor： Yi Yu Lin ,  Po Kai Hsu ,  Chun-Hao Wang ,  Yu-Ru Yang ,  Ju Chun Fan ,  Chung Yi Chiu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

公开(公告)号：US11631803B2

公开(公告)日：2023-04-18

申请号：US17134485

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

公开(公告)号：US11631761B2

公开(公告)日：2023-04-18

申请号：US17676867

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

公开(公告)号：US20230113989A1

公开(公告)日：2023-04-13

申请号：US18081646

申请日：2022-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, a second electrode, a first dielectric layer and a second dielectric layer. The semiconductor channel layer is disposed on the substrate. The semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The second electrode is disposed at another side of the gate electrode. The second electrode includes a body portion and a vertical extension portion. The first dielectric layer is disposed between the vertical extension portion of the first electrode and the semiconductor channel layer. The second dielectric layer is disposed between the vertical extension portion of the second electrode and the semiconductor channel layer.

公开(公告)号：US20230112917A1

公开(公告)日：2023-04-13

申请号：US17515541

申请日：2021-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H01L21/308 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/306 ,  H01L29/66

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US11626500B2

公开(公告)日：2023-04-11

申请号：US17369985

申请日：2021-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US11621271B2

公开(公告)日：2023-04-04

申请号：US17177164

申请日：2021-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H01L21/28 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20230101900A1

公开(公告)日：2023-03-30

申请号：US18077191

申请日：2022-12-07

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US20230099443A1

公开(公告)日：2023-03-30

申请号：US17505663

申请日：2021-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hon-Huei Liu ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L27/11507

Abstract: The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.