公开(公告)号：US09779473B2

公开(公告)日：2017-10-03

申请号：US15202143

申请日：2016-07-05

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06F9/48 ,  G06F12/128 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

公开(公告)号：US20170004598A1

公开(公告)日：2017-01-05

申请号：US15202143

申请日：2016-07-05

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

Abstract translation: 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

公开(公告)号：US20250117060A1

公开(公告)日：2025-04-10

申请号：US18883328

申请日：2024-09-12

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/26 ,  G06F12/0875

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US12260470B2

公开(公告)日：2025-03-25

申请号：US18536581

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu

IPC: G06F15/16 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0888 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

公开(公告)号：US20250095099A1

公开(公告)日：2025-03-20

申请号：US18893028

申请日：2024-09-23

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

公开(公告)号：US12205192B2

公开(公告)日：2025-01-21

申请号：US17398480

申请日：2021-08-10

Applicant: INTEL CORPORATION

Inventor： Balaji Vembu ,  Nikos Kaburlasos ,  Josh B. Mastronarde

IPC: G06T1/20 ,  G06F1/3203 ,  G06F1/3231 ,  G06F1/3234 ,  G06T1/60

Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

公开(公告)号：US12141891B2

公开(公告)日：2024-11-12

申请号：US18466991

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F17/16 ,  G06F18/2136 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  H03M7/30

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

公开(公告)号：US12131402B2

公开(公告)日：2024-10-29

申请号：US17749275

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

公开(公告)号：US12112397B2

公开(公告)日：2024-10-08

申请号：US18334733

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

公开(公告)号：US12086602B2

公开(公告)日：2024-09-10

申请号：US18365595

申请日：2023-08-04

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06F9/54 ,  G06F12/0842 ,  G06F12/0866 ,  G06F12/0897 ,  G06F15/16 ,  G06F15/76 ,  G06T1/60

CPC classification number: G06F9/3851 ,  G06F9/46 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/522 ,  G06F9/545 ,  G06F12/0842 ,  G06F12/0866 ,  G06F12/0897 ,  G06F15/16 ,  G06F15/76 ,  G06T1/20 ,  G06T1/60 ,  G06F2209/5018 ,  G06T2200/28

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.