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    METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING
    271.
    发明申请
    METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING 审中-公开

    公开(公告)号：US20200371921A1

    公开(公告)日：2020-11-26

    申请号：US16882264

    申请日：2020-05-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

    IPC: G06F12/0811 ,  G06F12/0891 ,  G06F9/54 ,  G06F9/30

    Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

    WRITE STREAMING IN A PROCESSOR
    272.
    发明申请
    WRITE STREAMING IN A PROCESSOR 审中-公开

    公开(公告)号：US20200371917A1

    公开(公告)日：2020-11-26

    申请号：US16874331

    申请日：2020-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson

    IPC: G06F12/0811 ,  G06F9/54 ,  G06F1/14

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.

    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD
    276.
    发明申请
    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20180246855A1

    公开(公告)日：2018-08-30

    申请号：US15905250

    申请日：2018-02-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Donald Edward Steiss ,  Timothy David Anderson ,  Kai Chirca

    IPC: G06F17/16

    Abstract: A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

    Vector SIMD VLIW Data Path Architecture
    278.
    发明申请
    Vector SIMD VLIW Data Path Architecture 审中-公开
    矢量SIMD VLIW数据路径架构

    公开(公告)号：US20150154024A1

    公开(公告)日：2015-06-04

    申请号：US14327084

    申请日：2014-07-09

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30112 ,  G06F9/3893

    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

    Abstract translation: 特别适用于各种操作数宽度和数据大小的单指令多数据（SIMD）操作的超长指令字（VLIW）数字信号处理器。 向量比较指令比较第一和第二操作数并存储比较位。 伴随向量条件指令根据相应谓词数据寄存器位的状态执行条件操作。 谓词单元对包括一元操作和二进制操作的至少一个谓词数据寄存器中的数据执行数据处理操作。 谓词单元还可以在通用数据寄存器文件和谓词数据寄存器文件之间传送数据。

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