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    Elements for in-memory compute
    282.
    发明授权
    Elements for in-memory compute 有权

    公开(公告)号：US11474788B2

    公开(公告)日：2022-10-18

    申请号：US16890870

    申请日：2020-06-02

    Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

    IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

    Low-power tilt-compensated pointing method and corresponding pointing electronic device
    283.
    发明授权
    Low-power tilt-compensated pointing method and corresponding pointing electronic device 有权

    公开(公告)号：US11474621B2

    公开(公告)日：2022-10-18

    申请号：US16932467

    申请日：2020-07-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Stefano Paolo Rivolta ,  Federico Rizzardini ,  Lorenzo Bracco

    IPC: G06F3/0346 ,  G06F3/01 ,  G06F3/038 ,  G06F3/0354

    Abstract: An embodiment pointing method to generate screen-frame displacement data based on 3D-space movements of a pointing electronic device, comprises receiving a gravity vector (g), having components (gx, gy, gz) corresponding to respective projections of gravity acceleration ({right arrow over (g)}) on three axes (X, Y, Z) of a 3D reference system associated with the pointing electronic device, generated by a sensor-fusion algorithm from joint processing of an acceleration signal, indicative of acceleration acting on the pointing electronic device along the three axes, and of a gyroscope signal (Gyro), indicative of angular rate of rotation of the pointing electronic device around the three axes. The method further comprises implementing a roll-compensation of the gyroscope signal (Gyro) as a function of the gravity vector (g) to determine a roll-compensated gyroscope signal (Gyro′); and generating the screen-frame displacement data based on the roll-compensated gyroscope signal (Gyro′).

    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF
    285.
    发明申请
    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF 有权

    公开(公告)号：US20220319598A1

    公开(公告)日：2022-10-06

    申请号：US17697846

    申请日：2022-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Roberto Bregoli ,  Vikas Rana

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/1156 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

    Presence detection device and method
    287.
    发明授权
    Presence detection device and method 有权

    公开(公告)号：US11462086B2

    公开(公告)日：2022-10-04

    申请号：US17207073

    申请日：2021-03-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Enrico Rosario Alessi ,  Fabio Passaniti

    IPC: G08B13/19 ,  G08B13/22

    Abstract: In accordance with an embodiment, a detection device includes: an infrared temperature sensor configured to provide a temperature signal associated with an heat emission of at least one individual within a monitored area; an electrostatic-charge-variation sensor configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the at least one individual; and a processing unit, coupled to the infrared temperature sensor and to the electrostatic-charge-variation sensor, the processing unit configured to detect a presence of the at least one individual within the monitored area by receiving the temperature signal and the charge-variation signal, and jointly processing the temperature signal and charge.

    Digital signal processing circuit and corresponding method of operation
    288.
    发明授权
    Digital signal processing circuit and corresponding method of operation 有权

    公开(公告)号：US11461257B2

    公开(公告)日：2022-10-04

    申请号：US17339083

    申请日：2021-06-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Lorenzo Re Fiorentin ,  Giampiero Borgonovo

    IPC: G06F13/28 ,  G06F9/46 ,  G06F13/37 ,  G06F13/372 ,  G06F17/14

    Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

    PIECEWISE LINEAR FUNCTION GENERATING ELECTRONIC CIRCUIT, CORRESPONDING GENERATOR, AMPLIFIER, METHOD AND COMPUTER PROGRAM PRODUCT
    289.
    发明申请
    PIECEWISE LINEAR FUNCTION GENERATING ELECTRONIC CIRCUIT, CORRESPONDING GENERATOR, AMPLIFIER, METHOD AND COMPUTER PROGRAM PRODUCT 有权

    公开(公告)号：US20220308615A1

    公开(公告)日：2022-09-29

    申请号：US17702362

    申请日：2022-03-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barbaro MARANO ,  Mario CHIRICOSTA

    IPC: G05F3/26 ,  H03F3/45

    Abstract: A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.

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