公开(公告)号：US09799649B2

公开(公告)日：2017-10-24

申请号：US15009760

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin.

公开(公告)号：US20170294436A1

公开(公告)日：2017-10-12

申请号：US15627329

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

公开(公告)号：US09786564B2

公开(公告)日：2017-10-10

申请号：US15253805

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US09773912B2

公开(公告)日：2017-09-26

申请号：US15089380

申请日：2016-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.

公开(公告)号：US09768170B2

公开(公告)日：2017-09-19

申请号：US15071224

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, a first gate, a second gate, an opening and a first dielectric layer. The substrate includes a first semiconductor fin, a second semiconductor fin and a trench between the first semiconductor fin and the second semiconductor fin. The insulator is disposed in the trench. The first gate is disposed on the first semiconductor fin. The second gate is disposed on the second semiconductor fin. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first gate and the second gate, wherein the first dielectric layer includes an air gap therein.

公开(公告)号：US20170263604A1

公开(公告)日：2017-09-14

申请号：US15063907

申请日：2016-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088

Abstract: The method may include steps of receiving a device that includes a source/drain, a gate, a gate spacer formed on a sidewall of the gate, and a dielectric component formed over the source/drain, forming a recess in a top surface of the dielectric component; forming a dielectric layer over the top surface of the dielectric component and over the recess, such that a portion of the dielectric layer assumes a recessed shape; and etching a contact hole through the dielectric layer and the dielectric component, the contact hole exposing the source/drain.

公开(公告)号：US20170256458A1

公开(公告)日：2017-09-07

申请号：US15473627

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/66545

Abstract: Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first region, and a first end sidewall of the first gate is faced to a second end sidewall of the second gate. Third and fourth gates are on the substrate in the second region, and a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate. A dielectric layer is between the first and second gates and between the third and fourth gates. The first and second regions have different pattern densities, and an included angle between the substrate and a sidewall of the dielectric layer between the first and second gates is different from an included angle between the substrate and a sidewall of the dielectric layer between the third and fourth gates.

公开(公告)号：US09722079B2

公开(公告)日：2017-08-01

申请号：US14883636

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US09716093B1

公开(公告)日：2017-07-25

申请号：US15062224

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/4983

Abstract: A semiconductor device including a substrate, insulators, a gate dielectric layer, a first gate structure and a second gate structure is provided. The substrate includes trenches, a first semiconductor fin and a second semiconductor fin. The first gate structure is disposed on the gate dielectric layer and partially covers the first semiconductor fin. The first gate structure includes a first metal gate and a first dielectric cap covering the first metal gate. The second gate structure is disposed on the gate dielectric layer and partially covers the second semiconductor fin. The second gate structure includes a second metal gate and a second dielectric cap covering the second metal gate. Work function of the first metal gate is smaller than work function of the second metal gate and thickness of the first dielectric cap is smaller than thickness of the second dielectric cap.

公开(公告)号：US20170194247A1

公开(公告)日：2017-07-06

申请号：US14985157

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/7685 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295

Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.