公开(公告)号：US08082416B2

公开(公告)日：2011-12-20

申请号：US12859013

申请日：2010-08-18

Applicant: Gaurav Singh ,  Dave Hass ,  Daniel Chen

Inventor： Gaurav Singh ,  Dave Hass ,  Daniel Chen

IPC: G06F12/08

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract translation: 呈现用于将虚拟地址转换成物理地址的扩展翻译后备缓冲器（eTLB），eTLB包括具有多个物理地址的物理存储器地址存储器，虚拟存储器地址存储器，被配置为存储对应的多个虚拟存储器地址 物理地址，虚拟存储器地址存储包括集合关联存储器结构（SAM）和内容可寻址存储器（CAM）结构; 以及用于确定所请求的地址是否存在于所述虚拟存储器地址存储器中的比较电路，其中所述eTLB被配置为接收用于识别所述SAM结构和所述CAM结构的索引寄存器，并且其中所述eTLB被配置为接收用于 提供与所述多个虚拟存储器地址对应的虚拟页码。

公开(公告)号：US08073856B2

公开(公告)日：2011-12-06

申请号：US12171099

申请日：2008-07-10

Applicant: Srinivasan Venkatachary ,  Pankaj Gupta

Inventor： Srinivasan Venkatachary ,  Pankaj Gupta

IPC: G06F17/00

CPC classification number: H04L45/00 ,  G06F17/30625 ,  H04L45/7457 ,  Y02D10/45 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub-database is pointed to by a pointer within a pointer table. When performing a longest-match search of incoming addresses, a longest prefix matching algorithm can be used to find the longest match among specialized “spear prefixes” stored in the pointer table. After the longest spear prefixes are found, the pointer table will direct the next search within a sub-database pointed to by that spear prefix. Another longest-match search can be performed for database prefixes (or simply “prefixes”) within the sub-database selected by the pointer. Only the sub-database of interest will, therefore, be searched and all other sub-databases are not accessed. Using a precursor pointer and a sub-database of optimally bounded size and number ensures power consumption be confined only to the sub-database being accessed, and that higher speed lookup operations can be achieved since only the sub-database of interest is being searched.

Abstract translation: 提供了一种形成转发数据库的方法，装置和存储介质产品，并且用于使用形成的数据库更有效地并且快速地通过计算机网络路由数据包。 转发数据库被安排成多个子数据库。 每个子数据库由指针表中的指针指向。 当对输入地址执行最长匹配搜索时，可以使用最长的前缀匹配算法来找到存储在指针表中的专用“矛前置”之间的最长匹配。 在找到最长的矛前缀之后，指针表将指示由该矛前缀指向的子数据库中的下一个搜索。 可以在由指针选择的子数据库中的数据库前缀（或简称“前缀”）执行另一最长匹配搜索。 因此，仅搜索感兴趣的子数据库，并且不会访问所有其他子数据库。 使用前导指针和具有最大有界大小和数量的子数据库，确保功耗仅限于正在访问的子数据库，并且可以实现更高速度的查找操作，因为仅搜索感兴趣的子数据库。

公开(公告)号：US08041757B2

公开(公告)日：2011-10-18

申请号：US11897941

申请日：2007-08-31

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: G06F17/10

CPC classification number: H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03484

Abstract: A method of signal processing comprises receiving an unknown input signal that includes a distorted component and an undistorted component, the unknown input signal having a sampling rate of R; and performing self-linearization based at least in part on the unknown signal to obtain an output signal that is substantially undistorted, including by generating a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1.A digital signal processing system comprises an input terminal configured to receive an unknown input signal that includes a distorted component and an undistorted component, the unknown input signal having a sampling rate of R; and an adaptive self-linearization module coupled to the input terminal, configured to perform self-linearization based at least in part on the unknown input signal to obtain an output signal that is substantially undistorted, wherein the adaptive self-linearization module includes a replica distortion signal generator configured to generate a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1.

Abstract translation: 一种信号处理方法包括接收包括失真分量和未失真分量的未知输入信号，未知输入信号具有采样率R; 以及至少部分地基于所述未知信号来执行自线性化，以获得基本上未失真的输出信号，包括通过产生基本上类似于所述失真分量的复制失真信号，所述复制失真信号至少部分地基于 目标分量具有R / L的采样率，L是大于1的整数。数字信号处理系统包括被配置为接收包括失真分量和未失真分量的未知输入信号的输入端，所述未知输入信号具有 抽样率为R; 以及耦合到所述输入端子的自适应自线性化模块，被配置为至少部分地基于所述未知输入信号执行自线性化，以获得基本上未失真的输出信号，其中所述自适应自线性化模块包括复制失真 信号发生器被配置为产生基本上类似于失真分量的复制失真信号，所述生成至少部分地基于具有R / L的采样率的目标分量，L是大于1的整数。

公开(公告)号：US08018751B1

公开(公告)日：2011-09-13

申请号：US12504523

申请日：2009-07-16

Applicant: Dinesh Maheshwari ,  Andrew Wright ,  Bin Jiang ,  Bartosz Banachowicz

Inventor： Dinesh Maheshwari ,  Andrew Wright ,  Bin Jiang ,  Bartosz Banachowicz

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Abstract translation: 形成在具有排列成行和列的单元的TCAM存储单元阵列中的三元内容可寻址存储器（TCAM）单元电路可以包括具有第一和第二数据路径的第一存储电路，具有第三和第四数据路径的第二存储电路，以及 比较电路。 在列方向上不超过四条导线与TCAM电池有直接电连接。 这样的导线可以包括耦合到第一数据路径和第三数据路径的第一位线和耦合到第二数据路径和第四数据路径的第二位线。

公开(公告)号：US08000412B1

公开(公告)日：2011-08-16

申请号：US11756139

申请日：2007-05-31

Applicant: Marc Loinaz

Inventor： Marc Loinaz

IPC: H03K5/159

CPC classification number: H04L25/4904 ,  H04L25/0272

Abstract: The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.

Abstract translation: 本发明涉及采用差分归零信令的低功率串行链路。 与一些实施例一致的接收机电路包括用于接收形成差分归零信令的差分串行数据信号的输入电路和时钟恢复电路。 时钟恢复电路耦合到输入电路，并且包括被配置为通过使用所述差分串行数据信号产生时钟信号的逻辑门。

公开(公告)号：US07991977B2

公开(公告)日：2011-08-02

申请号：US11961910

申请日：2007-12-20

Applicant: David T. Hass ,  Basab Mukherjee

Inventor： David T. Hass ,  Basab Mukherjee

IPC: G06F12/00 ,  G06F15/173

CPC classification number: G06F12/1036 ,  G06F12/0813 ,  H04L49/00

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07944829B2

公开(公告)日：2011-05-17

申请号：US11093184

申请日：2005-03-28

Applicant: Paolo Narvaez ,  Murat Bog

Inventor： Paolo Narvaez ,  Murat Bog

IPC: G08C15/00

CPC classification number: H04L47/10 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/326 ,  H04L47/6215 ,  H04L49/90 ,  H04L49/9047

Abstract: A system and method for policing of access to resources in a heterogeneous data redirection device is disclosed. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource. The invention uses a combination of different metrics each of which utilizes a different version of RED. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet requests access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.

Abstract translation: 公开了一种用于在异构数据重定向设备中对资源的访问进行管理的系统和方法。 本发明利用随机早期检测来确定给定的分组是否应被丢弃或接受到资源中。 本发明使用不同的度量的组合，其中每个都使用不同版本的RED。 方案可以包括每流加权RED度量，全球RED度量和公平共享池度量，其中共享资源分配在动态上依赖于数据包请求访问时的用户数量。 这些度量可以通过多种方式进行组合，以产生最终丢弃或接受传入数据包的决定，以使其不访问资源。

公开(公告)号：US07933885B1

公开(公告)日：2011-04-26

申请号：US12110103

申请日：2008-04-25

Applicant: Cristian Lambiri ,  Paul Nadj

Inventor： Cristian Lambiri ,  Paul Nadj

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F7/02 ,  G06F17/30327

Abstract: A search engine searches a database for key candidates having a longest matching prefix with a search key. The search engine includes first stage decoders each having a matrix of interconnected cells for identifying preliminary candidate keys in the database. The search engine also includes a second stage decoder having a matrix of interconnected cells for identifying secondary candidate keys from the preliminary candidate keys. Additionally, the search engine includes a longest candidate prefix module to determine whether one of the secondary candidate keys matches the search key. In some embodiments, the search engine includes a longest prefix match module for identifying the secondary candidate key having a longest matching prefix with the search key.

Abstract translation: 搜索引擎使用搜索关键字搜索具有最长匹配前缀的关键候选者的数据库。 搜索引擎包括每个具有用于识别数据库中的预备候选键的互连单元矩阵的第一级解码器。 搜索引擎还包括具有互连小区的矩阵的第二级解码器，用于从预备候选键识别辅助候选键。 另外，搜索引擎包括最长候选前缀模块，用于确定辅助候选键中的一个是否匹配搜索关键字。 在一些实施例中，搜索引擎包括最长前缀匹配模块，用于识别具有与搜索关键字具有最长匹配前缀的次候选密钥。

公开(公告)号：US20110085553A1

公开(公告)日：2011-04-14

申请号：US12946780

申请日：2010-11-15

Applicant: Kai-Yeung (Sunny) SIU ,  Brian Hang Wai YANG ,  Mizanur M. RAHMAN

Inventor： Kai-Yeung (Sunny) SIU ,  Brian Hang Wai YANG ,  Mizanur M. RAHMAN

IPC: H04L12/56

CPC classification number: H04Q3/68 ,  H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/60 ,  H04L49/606 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5681

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.

Abstract translation: 网络交换机包括用于接收具有一组单元的数据流的输入层。 每个小区包括指定目的地设备的数据和报头。 输入层包括一组输入层电路。 该组输入层电路的选定输入层电路接收数据流。 所选择的输入层电路包括与一组目的地设备相对应的一组队列。 所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。 所选择的队列对应于由所选小区的头部指定的所选目的地设备。 中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。 所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。 输出层包括与目标设备组对应的一组输出层电路。 所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

公开(公告)号：US07920397B1

公开(公告)日：2011-04-05

申请号：US12771657

申请日：2010-04-30

Applicant: Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/12 ,  G11C11/419 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/1204

Abstract: A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration mode, a leakage-free sense operation is performed to determine the differential voltage generated on the bit lines in response to a data value. Then, a leakage-susceptible test read operation is performed to determine the differential voltage generated on the bit lines in response to the data value. A detection circuit measures the difference between the differential voltages generated in the leakage-free and leakage-susceptible test read operations to generate a compensation signal, which subsequently adjusts the bit line compensation current during the normal mode.

Abstract translation: 存储器件在校准模式下工作，在该校准模式期间测量位线泄漏电流的影响并且在正常模式下操作，在正常模式期间，根据校准模式的结果调整位线电流以补偿泄漏。 在校准模式中，执行无泄漏检测操作以确定响应于数据值在位线上产生的差分电压。 然后，执行泄漏敏感的测试读取操作，以响应于数据值来确定在位线上产生的差分电压。 检测电路测量在无泄漏和易泄漏的测试读取操作中产生的差分电压之间的差异，以产生补偿信号，随后在正常模式期间调整位线补偿电流。