公开(公告)号：US10452478B2

公开(公告)日：2019-10-22

申请号：US15794164

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

IPC: G11C29/00 ,  G06F11/10

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US10418089B2

公开(公告)日：2019-09-17

申请号：US15389407

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F1/04 ,  G06F13/42 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US10404258B2

公开(公告)日：2019-09-03

申请号：US15796608

申请日：2017-10-27

Applicant: Rambus Inc.

Inventor： Marko Aleksić ,  Brian S. Leibowitz

IPC: H03B5/08 ,  H03B5/18 ,  H03L1/00 ,  H03L7/24 ,  H03K3/03 ,  H03L7/083

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

公开(公告)号：US10388396B2

公开(公告)日：2019-08-20

申请号：US15506621

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US10380056B2

公开(公告)日：2019-08-13

申请号：US15647983

申请日：2017-07-12

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/00 ,  G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US10325636B1

公开(公告)日：2019-06-18

申请号：US15945235

申请日：2018-04-04

Applicant: Rambus Inc.

Inventor： Neeraj Purohit ,  Navin Kumar Mishra ,  Anirudha Shelke

IPC: G11C7/22 ,  H03K5/135

Abstract: A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

公开(公告)号：US10320534B2

公开(公告)日：2019-06-11

申请号：US15872885

申请日：2018-01-16

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04B3/46 ,  H04L1/20 ,  H04L7/00 ,  H04L7/10 ,  G01R31/317 ,  H04L1/24

Abstract: An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.

公开(公告)号：US10284825B2

公开(公告)日：2019-05-07

申请号：US15244297

申请日：2016-08-23

Applicant: Rambus Inc.

Inventor： Jay Endsley

IPC: H04N9/04 ,  H04N5/225 ,  G02B13/16 ,  G02B5/18

Abstract: An imaging system includes a refractive optical element and one or more diffractive optical gratings disposed over a two-dimensional array of photosensitive pixels. The different gratings present different patterns and features that are tailored to produce point-spread responses that emphasize different properties of an imaged scene. The different responses are captured by the pixels, and data captured from the responses can be used separately or together to analyze aspects of the scene. The imaging systems can include circuitry to analyze the image data, and to support modes that select between point-spread responses, selections of the pixels, and algorithms for analyzing image data.

公开(公告)号：US10277843B2

公开(公告)日：2019-04-30

申请号：US15589149

申请日：2017-05-08

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/355 ,  H04N5/378 ,  H04N5/347 ,  H04N5/3745 ,  H01L27/146 ,  H04N5/374 ,  H01L31/113

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

公开(公告)号：US10274652B2

公开(公告)日：2019-04-30

申请号：US15423892

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jay Endsley ,  Thomas Vogelsang

IPC: H04N5/225 ,  G02B5/18 ,  H04N5/335

Abstract: An imaging device uses a grating to produce an interference pattern for capture by a photodetector array. Digital photographs and other image information can then be extracted from the pattern. An integrated processor locally supports this extraction by upsampling the captured interference pattern and deconvolving the upsampled pattern with an image-calculation parameter set that represents the grating at a resolution greater than that provided by the photodetector array. Deconvolving the upsampled pattern with a high-resolution parameter increases the resolution of extracted image information.