公开(公告)号：US20140254206A1

公开(公告)日：2014-09-11

申请号：US13947820

申请日：2013-07-22

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yingyang Ou ,  Qingyi Huang ,  Renjian Xie ,  Ling Ren

IPC: H02M3/335

CPC classification number: H02M3/33592 ,  Y02B70/1475

Abstract: In certain example embodiments, a system is provided that includes a circuit. The system also includes a reverse current control module that provides an isolated power supply in order to protect one or more devices in a power chain during one or more testing activities having one or more requirements.

Abstract translation: 在某些示例性实施例中，提供了包括电路的系统。 该系统还包括反向电流控制模块，其提供隔离的电源，以便在具有一个或多个要求的一个或多个测试活动期间保护功率链中的一个或多个设备。

公开(公告)号：US20140253223A1

公开(公告)日：2014-09-11

申请号：US13793543

申请日：2013-03-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Patrick J. Meehan ,  Mark T. Kelly ,  Christopher Peter Hurrell ,  Thomas Anthony Conway ,  Donal O'Sullivan ,  Michael Hennessy ,  William Hunt

IPC: H03K17/00

CPC classification number: H03H21/0007 ,  G06F1/26 ,  H03K17/00 ,  H03K17/161 ,  H03M1/0626 ,  H03M1/12

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract translation: 一种信号处理装置，包括在第一时间段内执行信号处理功能的电路，所述信号处理装置包括或者与所述信号处理装置的电源中的开关或滤波器相关联，以便断开所述信号处理装置 信号处理装置，或者在与第一时间段的至少一部分一致的第二时间段期间对电源进行滤波。

公开(公告)号：US20140247031A1

公开(公告)日：2014-09-04

申请号：US13782223

申请日：2013-03-01

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： SONG QIN

IPC: H02M1/32 ,  H02M3/156

CPC classification number: H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A negative current protection system for a low side switching converter FET, for use with a switching converter arranged to operate high and low side FETs connected to an output inductor to produce an output voltage. The negative current protection system comprises a current sensing circuit which produces an output Vcs that varies with the current in the high side FET, a negative current threshold generator which produces a threshold signal −Ith which represents the maximum negative current to which the low side FET is to be subjected, and a comparison circuit arranged to compare the valley portion of Vcs and −Ith and to set a flag if Vcs

Abstract translation: 一种用于低侧开关转换器FET的负电流保护系统，用于与连接到输出电感器的高低侧FET连接以产生输出电压的开关转换器。 负电流保护系统包括电流检测电路，其产生随着高侧FET中的电流而变化的输出Vcs;产生阈值信号的负电流阈值发生器，其表示低边FET的最大负电流 并且比较电路被布置为比较Vcs和-Ith的谷部分，并且在开关周期中的预定时间（通常在转换器的消隐时间之后）设置Vcs <-Ith的标志。 当标志置位时，系统优选地通过调节开关FET的操作来减小负电流来进行响应。

公开(公告)号：US08823419B1

公开(公告)日：2014-09-02

申请号：US13792835

申请日：2013-03-11

Applicant: Analog Devices Technology

Inventor： Finbarr O'Leary ,  Michael Edward Bradley ,  Naiqian Ren ,  George R. Spalding ,  Nigel David Brooke

IPC: H03K5/153

CPC classification number: H03K5/22

Abstract: A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vref1 is provided at a third node and a voltage Vref2 referenced to Vref1 is at a fourth node. A hysteresis hyst1 is switchably connected between the third and first nodes, and a hysteresis hyst2 is switchably connected between the fourth and second nodes. Hyst1 and hyst2 are switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

Abstract translation: 乒乓比较器电压监视电路，其包括具有连接到要监视的电压Vin的输入的第一和第二比较器，以及分别连接到第一和第二节点的第二输入。 复用器响应于周期性控制信号将第一和第二比较器输出交替耦合到输出。 在第三节点处提供地参考电压Vref1，并且参考Vref1的电压Vref2在第四节点处。 迟滞hyst1可切换地连接在第三节点和第一节点之间，并且滞后hyst2可切换地连接在第四节点和第二节点之间。 当Mux输出由于Vin上升而切换时，Hyst1和hyst2被切换，并且当多路复用器输出由于Vin下降而切换时，Hyst1和hyst2被切换。

公开(公告)号：US20140239925A1

公开(公告)日：2014-08-28

申请号：US13775820

申请日：2013-02-25

Applicant: Analog Devices Technology

Inventor： Hirohisa Tanabe ,  Kenji Tomiyoshi

IPC: H02M3/158

CPC classification number: H02M3/1582 ,  H02M3/156 ,  H02M2001/0009

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract translation: 一种与开关转换器一起使用的电感器电流仿真电路，其中调节输出电压包括将输出与输出电压和参考电压之间的差值进行比较，其中的“斜坡”信号模拟输出电感器中的电流。 电流感测电路产生随着在“关断”时间期间导通的开关元件中的电流而变化的输出，仿真电流发生器电路在“断开”和“打开”时间期间产生“斜坡”信号，a 比较器电路将“斜坡”信号与至少一个随感测电流变化的阈值电压进行比较，并在“斜坡”超过阈值时切换输出，反馈电路产生一个输出，每次输出调整“斜坡”信号 比较器电路输出切换直到“斜坡”信号不再超过阈值电压。

公开(公告)号：US20140232580A1

公开(公告)日：2014-08-21

申请号：US13770064

申请日：2013-02-19

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Avinash Gutta ,  Alan Gillespie ,  Roderick McLachlan

IPC: H03K3/356 ,  H03M1/66

CPC classification number: H03K3/356139 ,  H03K17/00 ,  H03K17/16 ,  H03M1/66

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract translation: 数据转换器可以包括电阻器网络，连接到电阻器网络的开关网络，并且具有多个开关电路，每个开关电路各自具有NMOS和PMOS开关晶体管，以及电压发生器，用于产生用于驱动栅极的驱动电压 至少一个开关电路的NMOS或PMOS开关晶体管中的至少一个。 电压发生器可以包括第一和第二对晶体管，每对晶体管具有连接的控制端子，并且连接到第二NMOS或PMOS晶体管，第一或第二电阻器以及另一对晶体管。 第一和第二电阻器可具有基本相等的电阻值。 第二NMOS与PMOS晶体管的宽比比可以与开关电路NMOS与PMOS晶体管的这一比例基本相等。

公开(公告)号：US20140204232A1

公开(公告)日：2014-07-24

申请号：US13749675

申请日：2013-01-24

Applicant: Yong Wang ,  Jianrong Chen ,  Yimiao Zhao ,  Youcheng Huang ,  Xiaoming Chi

Inventor： Yong Wang ,  Jianrong Chen ,  Yimiao Zhao ,  Youcheng Huang ,  Xiaoming Chi

IPC: H04N9/04

CPC classification number: H04N9/04 ,  G06T1/20 ,  H04N5/23229

Abstract: The present disclosure provides a stream processor, an associated stream controller and compiler, and associated methods for data processing, such as image processing. In some embodiments, a method includes defining a kernel pattern associated with an image frame, and processing the image frame using the defined kernel pattern. The method can further include generating a kernel switch lookup table based on the defined kernel pattern. In various implementations, the stream controller is operable to direct execution of kernels on the image frame according to the defined kernel pattern and the kernel switch lookup table.

Abstract translation: 本公开提供了流处理器，相关联的流控制器和编译器以及用于诸如图像处理的数据处理的相关联的方法。 在一些实施例中，一种方法包括定义与图像帧相关联的内核模式，以及使用所定义的内核模式来处理图像帧。 该方法还可以包括基于所定义的内核模式生成内核切换查找表。 在各种实现中，流控制器可操作以根据所定义的内核模式和内核切换查找表来直接在图像帧上执行内核。

公开(公告)号：US08786483B1

公开(公告)日：2014-07-22

申请号：US13830382

申请日：2013-03-14

Applicant: Frederick Carnegie Thompson ,  Barry Stakely

Inventor： Frederick Carnegie Thompson ,  Barry Stakely

IPC: H03M1/38

CPC classification number: H03M1/0836 ,  H03M1/125 ,  H03M1/462

Abstract: Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Abstract translation: 本发明的实施例可以提供用于校正与异步逐次逼近寄存器（SAR）模数转换器（ADC）中的过程，电压和温度效应相关联的定时误差的改进的装置和方法。 SAR ADC可以包括定时器，其包括可编程定时电路，其可以确保SAR ADC的不同部件根据定时方案工作。 定时电路的工作可能随过程，电压和温度而变化，这可能不利地影响SAR ADC的定时/精度。 ADC可以包括与SAR ADC相同的集成电路上提供的参考电路，该ADC可以为定时电路提供定时参考。 如果参考电路指示定时电路的运行速度比理想速度更快或更慢，则定时电路内的定时值可被修改以补偿这种变化。

公开(公告)号：US20140192560A1

公开(公告)日：2014-07-10

申请号：US13735481

申请日：2013-01-07

Applicant: Analog Devices Technology

Inventor： YINGYANG OU ,  RENJIAN XIE ,  HUAILIANG SHENG

IPC: H03K3/017 ,  H02M3/335

CPC classification number: H02M1/08 ,  H02M1/40 ,  H02M3/33507 ,  H02M3/33576 ,  H02M2007/4803 ,  H03K17/56

Abstract: A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

Abstract translation: 用于开关模式功率转换器的占空比平衡模块（DCBM）。 一个可能的半桥转换器实施例包括分别被驱动以在第一和第二方向通过第一和第二信号在第一和第二半周期期间传导电流的变压器。 当感测电流超过预定极限阈值时，电流限制机构调节第一和第二信号的占空比。 DCBM接收代表占空比的信号，如果没有通过电流限制机制进行修改，并且表示实际用于第一和第二信号的占空比的Dact-1和Dact-2信号，以及输出 信号Dbl-1和Dbl-2，其根据需要修改信号Dact-1和Dact-2，以动态平衡第一和第二信号的占空比，从而减少可能出现的变压器中的通量不平衡。

公开(公告)号：US20140132435A1

公开(公告)日：2014-05-15

申请号：US13841150

申请日：2013-03-15

Applicant: Dennis A. DEMPSEY

Inventor： Dennis A. DEMPSEY

IPC: H03M1/78

CPC classification number: H03M1/0872 ,  H03M1/682 ,  H03M1/765

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract translation: 本发明的实施例可以提供具有电荷增压的串联DAC。 串DAC可以包括多个串，例如MSB DAC和LSB DAC，用于将数字字转换成相应的模拟电压。 串DAC还可以包括充电提升系统，以在诸如MSB代码转换的代码转换期间将电荷耦合到DAC中或从DAC中耦合。 串DAC可以在制造前连接技术中进行操作，其中在进行新连接之前所有相关连接基本上都是开路的。 因此，充电提升可以缩短代码转换之间的串DAC中的阻抗元件的建立时间，并且可以显着地减少（或消除）毛刺。