公开(公告)号：US5745742A

公开(公告)日：1998-04-28

申请号：US574804

申请日：1995-12-19

申请人： David W. Selway ,  David A. Bowman ,  Donald R. Kesner ,  James H. Phillips

发明人： David W. Selway ,  David A. Bowman ,  Donald R. Kesner ,  James H. Phillips

IPC分类号： G06F1/12 ,  G06F1/10

CPC分类号： G06F1/12

摘要： A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the clock and definer signals which are to "take over" are also at the predetermined logic level.

摘要翻译： 包括能够独立运行的两个系统的冗余计算机系统。 两个系统相应地采用两个独立的时钟产生和分配（CGD）单元，每个单元发出时钟和时钟定义信号。 当两个系统分离时，每个系统由其自己的CGD单元产生的时钟和定义信号控制。 当两个系统合并时，一个CGD单元被指定为主机，其时钟和定义信号驱动冗余系统的两侧。 每个CGD单元中包含的特殊逻辑可确保从主机到从机（或从机）到主机的运行无变化。 该特殊逻辑包括当本地时钟和定义信号均处于预定逻辑电平时，在本地时钟和定义信号上暂时保持暂时保持，这些信号在开关被使用时正在使用。 保持继续，直到要“接管”的时钟和定义信号也处于预定的逻辑电平。

公开(公告)号：US5636371A

公开(公告)日：1997-06-03

申请号：US473476

申请日：1995-06-07

申请人： Kin C. Yu

发明人： Kin C. Yu

IPC分类号： H04L12/46 ,  H04L29/06 ,  H04L29/08 ,  G06F13/00 ,  G06F15/163 ,  G06F15/177

CPC分类号： H04L12/46 ,  H04L12/4641 ,  H04L29/06 ,  H04L69/161 ,  H04L69/162 ,  H04L69/163 ,  H04L69/16 ,  H04L69/32

摘要： A local host data processing system operating under the control of a local host operating system includes components of a hosted operating system. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which the hosted operating system is attached. The mechanism transforms the well-known port identifier of each inbound packet into a non-well-known port identifier in addition to other station address identifier fields. It then redirects the transformed packet back to the IP layer of the stack for transfer to the appropriate well-known port application program of the hosted operating system. It reverses this operation for each reply packet which is also redirected back to the IP layer for forwarding to the remote system. This eliminates the need to specify additional protocol stacks and to provide additional communication hardware facilities for handling multiple instances of well-known port applications programs.

摘要翻译： 在本地主机操作系统的控制下操作的本地主机数据处理系统包括托管操作系统的组件。 主机操作系统还包括TCP / IP网络协议栈，其耦合到连接到局域网的主机系统的通信设施，用于与多个远程主机系统通信。 主机和托管操作系统共享相同的TCP / IP网络协议栈。 虚拟网络机制被配置在本地主机系统内以可操作地耦合到主机网络协议栈，并提供对公知的端口应用程序的访问。 当这样配置时，该机制用作托管操作系统附加到的另一个LAN。 该机制除了其他站地址标识符字段之外，还将每个入站分组的公知端口标识变换为非公知端口标识符。 然后，将转换的数据包重定向到堆栈的IP层，以转移到托管操作系统的相应的知名端口应用程序。 它将针对每个应答分组的操作进行反转，该分组也被重定向回到IP层以转发到远程系统。 这样就无需指定额外的协议栈，并提供额外的通信硬件设施来处理众所周知的端口应用程序的多个实例。

公开(公告)号：US5507000A

公开(公告)日：1996-04-09

申请号：US311797

申请日：1994-09-26

申请人： Wilbur L. Stewart ,  Ronald E. Lange ,  Richard L. Demers ,  Jeffrey D. Weintraub

发明人： Wilbur L. Stewart ,  Ronald E. Lange ,  Richard L. Demers ,  Jeffrey D. Weintraub

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/00 ,  G06F9/302

CPC分类号： G06F9/30101 ,  G06F9/3885

摘要： In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

摘要翻译： 在包含至少一个协处理器（例如浮点运算协处理器）的中央处理器中，除了基本的算术逻辑单元之外，还存在使累加器和辅助累加器寄存器的内容合理化的问题，而没有速度惩罚的负担 得到解决和解决。 这是通过向公共寄存器文件提供输入/输出访问并通过适当地将寄存器文件的控制切换到适当的处理单元来实现的。 堆栈中包含一个单独的共享累加器寄存器和一个单独的共享补充累加器寄存器以及其他可共享寄存器，如地址修改寄存器。 因此，累加器寄存器和补充累加器寄存器的内容始终是最新的，并且可用于中央处理器中的所有处理单元，而不需要首先执行合理化步骤。

公开(公告)号：US5491827A

公开(公告)日：1996-02-13

申请号：US181684

申请日：1994-01-14

申请人： Thomas O. Holtey

发明人： Thomas O. Holtey

IPC分类号： G06F12/14 ,  G06F21/02 ,  G06F21/22 ,  G06F21/24 ,  G06K17/00 ,  G06K19/073 ,  G07F7/10 ,  G06F15/20

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576

摘要： An application memory card system includes a secure memory card which can be operatively connected to communicate with a host mainframe microprocessor or hand held device host microprocessor via a standard interface. The secure memory card contains an application processor and an access control microprocessor (ACP), each of which connect through an internal bus to a number of non-volatile addressable memory chips, each organized into a plurality of blocks. Each microprocessor has an additional control signal line included in a control bus portion of its bus for specifying "Execute" access. An access discrimination logic unit which connects to the internal bus and to the non-volatile memory includes an access by type memory writable by the application processor under the control of the ACP for maintaining security. The access discrimination logic unit combines the "Execute" control access signal from a microprocessor with a signal designating the microprocessor source (e.g. external or internal) to define the type of memory access requested and transfers a control enabling signal as a function of the state of the selected stored access control bit indicating if the requested access is allowed to the addressed block.

摘要翻译： 应用存储卡系统包括可操作地连接以经由标准接口与主机主机微处理器或手持设备主机微处理器通信的安全存储卡。 安全存储卡包括应用处理器和访问控制微处理器（ACP），每个处理器和访问控制微处理器（ACP）通过内部总线连接到多个非易失性可寻址存储器芯片，每个被组织成多个块。 每个微处理器具有包含在其总线的控制总线部分中的附加控制信号线，用于指定“执行”访问。 连接到内部总线和非易失性存储器的访问鉴别逻辑单元包括在ACP的控制下可由应用处理器写入的类型存储器的访问以保持安全性。 访问鉴别逻辑单元将来自微处理器的“执行”控制访问信号与指定微处理器源（例如，外部或内部）的信号组合，以定义请求的存储器访问的类型，并将控制使能信号作为状态 所选择的存储的访问控制位指示所请求的访问是否被允许到所寻址的块。

公开(公告)号：US5491790A

公开(公告)日：1996-02-13

申请号：US231856

申请日：1994-04-22

申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/445 ,  G06F11/22 ,  G06F11/267

CPC分类号： G06F11/2236 ,  G06F11/22 ,  G06F9/4403

摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

公开(公告)号：US5487163A

公开(公告)日：1996-01-23

申请号：US148030

申请日：1993-11-04

申请人： James W. Keeley

发明人： James W. Keeley

IPC分类号： H03K5/135 ,  H03K5/13 ,  H03K19/003

CPC分类号： H03K5/135

摘要： A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period. The resulting output signal is directly applied to the input of another synchronously operated bistable device which stores the resulting output signal in response to the next occurring synchronous clock pulse corresponding to a time period which is greater than the time of the metastable time period, minimum delay of the logic part and preset of time of such bistable device.

摘要翻译： 方法和装置通过量化响应于第一同步时钟脉冲接收和存储异步信号的输入时钟双稳态器件的延迟量化同步操作器件的异步信号来提供异步信号的快速同步，使得这种输入时钟双稳态器件具有 亚稳态时间段小于预定的最大延迟周期。 输入时钟双稳态器件的输出信号直接连接到异步操作的逻辑电路部分的输入，该部分被选择以在预定的最小时间周期内提供与对输出信号执行逻辑运算的结果相对应的结果输出信号。 所得到的输出信号被直接施加到另一个同步操作的双稳态器件的输入端，该双稳态器件存储响应于下一个发生的同步时钟脉冲的输出信号，该时钟周期大于亚稳态时间段的时间段，最小延迟 的逻辑部分和这种双稳态设备的时间预设。

公开(公告)号：US5430862A

公开(公告)日：1995-07-04

申请号：US546348

申请日：1990-06-29

申请人： Steven S. Smith ,  Arnold J. Smith ,  Amy E. Gilfeather ,  Richard P. Brown ,  Thomas F. Joyce

发明人： Steven S. Smith ,  Arnold J. Smith ,  Amy E. Gilfeather ,  Richard P. Brown ,  Thomas F. Joyce

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30174 ,  G06F9/3879

摘要： The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

摘要翻译： 仿真器包括通过双向总线连接的第一和第二流水线级，用于执行通常由高度重叠的方式由不同/源计算机执行的源指令。 第一级包括仿真器芯片，其执行取出和解码存储在高速缓冲存储器中的每个源指令的功能，导致生成由第二级执行指令所需的多个向量地址。 第二级包括具有片上指令的高性能微处理器芯片和用于存储多个仿真子程序的数据高速缓存和在子程序执行期间取出的数据。 以流水线方式，仿真器芯片获取和解码每个源指令，其产生载入分支向量寄存器的向量分支地址，而微处理器芯片从每个先前解码的源获取并执行由总线传送的向量地址指定的仿真子程序 指令。

公开(公告)号：US5390196A

公开(公告)日：1995-02-14

申请号：US975311

申请日：1992-11-12

申请人： Brian D. Cecil ,  Edmund Kaemper

发明人： Brian D. Cecil ,  Edmund Kaemper

IPC分类号： H03M13/09 ,  G06F11/12

CPC分类号： H03M13/091

摘要： A fast and memory efficient software method for generating a checksum employing a 32-bit generator polynomial such as X.sup.32 +X.sup.26 +X.sup.23 +X.sup.22 +X.sup.16 +X.sup.12 +X.sup.11 +X.sup.10 +X.sup.8 +X.sup.7 +X.sup.5 +X.sup.4 +X.sup.2 +X.sup.1 +X.sup.0. This end is achieved by performing the successive steps of reversing the 32-bit polynomial, to obtain hexadecimal EDB88320 in the example, as an initial CRC; XORing the least significant unprocessed byte of the data set with the least significant 8-bit byte of the CRC as currently positioned to obtain X8, X7, X6, X5, X4, X3, X2, X1; shifting the CRC right eight bits; for Xi=X8 to X3, inclusive, successively testing the highest numbered unprocessed Xi bit to determine if it is a one or a zero; if the Xi bit being tested is a zero, the CRC remains unchanged for this bit; if the Xi bit being tested is a one, then XOR the shifted CRC with the a 32-bit pattern of Xi corresponding to EDB88320 shifted right zero places for X8, one place for X7, two places for X6, three places for X5, four places for X4 and five places for X3; for Xi=X2 and X1, successively testing the highest numbered unprocessed Xi bit to determine if it is a one or a zero; if the Xi bit being tested is a zero, the CRC remains unchanged for this bit; if the Xi bit being tested is a one, then XOR the shifted CRC with the a 32-bit pattern of Xi corresponding to a second predetermined polynomial, hexadecimal EE0E612C in the example, shifted right zero places for X2 and one place for X1; if bytes of the data set remain to be processed, looping to process the next byte; and if the last byte has been processed, appending the current value of the CRC to the data set as a checksum.

摘要翻译： 一种用于产生使用32位生成多项式（如X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + X0）的校验和的快速且高记忆效率的软件方法。 该结束是通过执行反转32位多项式的连续步骤来实现的，以获得该示例中的十六进制EDB88320作为初始CRC; 将目前定位为获得X8，X7，X6，X5，X4，X3，X2，X1的CRC的最低有效8位字节的数据集的最低有效未处理字节进行异或; 将CRC右移8位; 对于Xi = X8到X3，包括，连续测试最高编号的未处理的Xi位，以确定它是一个还是零; 如果被测试的Xi位为零，则该位保持不变; 如果被测试的Xi位是一个，则XOR与对应于EDB88320的X对应的32位模式的移位CRC移位到X8的右零位，X7的一个位置，X6的两个位置，X5的三个位置，四个 X3的地方和X3的五个地方; 对于Xi = X2和X1，连续测试最高编号的未处理的Xi位，以确定它是一个还是零; 如果被测试的Xi位为零，则该位保持不变; 如果正在测试的Xi位是一个，则XOR是具有对应于第二预定多项式的32位模式的移位CRC，在该示例中为十六进制EE0E612C，向右移位零位，X2为X1，X1为一; 如果数据集的字节仍然被处理，循环处理下一个字节; 并且如果最后一个字节已被处理，则将当前的CRC值附加到数据集作为校验和。

公开(公告)号：US5341501A

公开(公告)日：1994-08-23

申请号：US771582

申请日：1991-10-04

申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

IPC分类号： G06F13/368 ,  G06F9/46

CPC分类号： G06F13/368

摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

摘要翻译： 高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。 电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。 所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟 当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

公开(公告)号：US5295141A

公开(公告)日：1994-03-15

申请号：US629802

申请日：1990-12-19

申请人： George A. Person

发明人： George A. Person

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/28 ,  G01R31/28

CPC分类号： G06F11/0793 ,  G06F11/28 ,  G06F11/00 ,  G06F11/0751 ,  G06F11/0796

摘要： In order to prevent a logic circuit including a multi-stage temporary storage array having both valid and invalid state combinations from locking up in an inadvertently entered invalid state and from alternating between invalid state combinations, support logic circuitry is employed which is configured to force the array back to a valid state combination. The forcing operation may be alternatively undertaken immediately or in synchronism with the next succeeding clock pulse following entry into the invalid state combination. A specific valid state combination to be entered following entry into a specific invalid state may be predetermined.

摘要翻译： 为了防止包括具有有效和无效状态组合的多级临时存储阵列的逻辑电路锁定在无意中输入的无效状态和从无效状态组合之间交替出来，采用支持逻辑电路，其被配置为强制 阵列返回到有效的状态组合。 可以在进入无效状态组合之后立即或与下一个后续时钟脉冲同步地进行强制操作。 在进入特定无效状态之后要输入的特定有效状态组合可以被预先确定。