公开(公告)号：US10560092B2

公开(公告)日：2020-02-11

申请号：US16274844

申请日：2019-02-13

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc. ,  STMicroelectronics (Alps) SAS

Inventor： Vanni Poletto ,  David F. Swanson ,  Giovanni Luca Torrisi ,  Laurent Chevalier

IPC: H03K17/687 ,  G01R19/165 ,  G05B11/42

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

公开(公告)号：US10528422B2

公开(公告)日：2020-01-07

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US20190146868A1

公开(公告)日：2019-05-16

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US10217503B2

公开(公告)日：2019-02-26

申请号：US16151388

申请日：2018-10-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US09968700B2

公开(公告)日：2018-05-15

申请号：US14975200

申请日：2015-12-18

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joseph Edward Scheffelin ,  Dave S. Hunt ,  Timothy James Hoekstra ,  Faiz Sherman ,  Stephan Gary Bush

IPC: A61L9/03 ,  B05B17/06 ,  A61L2/00 ,  A61L9/00

CPC classification number: A61L9/03 ,  A61L2/00 ,  A61L9/00 ,  B05B17/0684

Abstract: One or more embodiments are directed to a microfluidic delivery system that dispenses a fluid. The microfluidic delivery system may be provided in a variety of orientations. In one embodiment, the microfluidic delivery system is vertical so that fluid being expelled opposes gravity. In another embodiment, the microfluidic delivery system is orientated sideways so that fluid being expelled has a horizontal component. In yet another embodiment, the microfluidic delivery system faces downward.

公开(公告)号：US09420163B2

公开(公告)日：2016-08-16

申请号：US14842238

申请日：2015-09-01

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Research & Development) Limited ,  STMicroelectronics Asia Pacific Pte Ltd

Inventor： Laurent Plaza ,  Olivier Lemarchand ,  Paul Varillon ,  Francesco Cascio ,  Duncan Hall ,  Sam Lee

IPC: H04N5/232 ,  G02B7/28 ,  H04N5/225 ,  H04N5/235 ,  H04N9/04

CPC classification number: H04N5/23212 ,  G02B7/28 ,  G02B7/365 ,  G02B7/40 ,  G03B13/36 ,  H04N5/2257 ,  H04N5/2351 ,  H04N9/045

Abstract: An autofocus method determines that a ranging device of a digital camera has failed in an attempt to provide a distance estimation. The ranging device provides one or more parameters indicating conditions related to the failure of the ranging device to provide the distance estimation. An autofocus sequence based on the one or more parameters is then performed.

Abstract translation: 自动对焦方法确定数字照相机的测距设备已经失败以试图提供距离估计。 测距设备提供一个或多个参数，其指示与测距设备的故障相关的条件以提供距离估计。 然后执行基于一个或多个参数的自动聚焦序列。

公开(公告)号：US20150083900A1

公开(公告)日：2015-03-26

申请号：US14493553

申请日：2014-09-23

Applicant: STMicroelectronics (Research & Development) Limited ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Adam Caley ,  Pierre-Jean Parodi-Keravec ,  Olivier Le Briz ,  Sandrine Lhostis

IPC: G01S17/46 ,  G01S7/481

CPC classification number: G01S7/4811 ,  G01S7/497 ,  G01S17/026 ,  G01S17/36

Abstract: A proximity sensor includes a radiation source configured to emit a primary radiation beam and a primary detector configured to pick up a reflected primary radiation beam. The radiation source is further configured to emit stray radiation. The sensor further includes a reference detector arranged to receive the stray radiation. The stray radiation may, for example, be emitted from either a side of the radiation source or a bottom of the radiation source.

Abstract translation: 接近传感器包括被配置为发射主辐射束的辐射源和被配置为拾取反射的一次辐射束的主检测器。 辐射源还被配置成发射杂散辐射。 传感器还包括布置成接收杂散辐射的参考检测器。 杂散辐射可以例如从辐射源的一侧或辐射源的底部发射。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US08285236B2

公开(公告)日：2012-10-09

申请号：US12505671

申请日：2009-07-20

Applicant: Antoine Hue ,  Gabriel Della-Monica ,  Florent Sibille

Inventor： Antoine Hue ,  Gabriel Della-Monica ,  Florent Sibille

IPC: H04B17/00 ,  H04B1/00 ,  H04L27/08

CPC classification number: H04L25/063

Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.

Abstract translation: 一种方法可以补偿射频接收装置中的直流（DC）偏移。 该方法可以包括将接收设备的模拟部分划分成多个区域，对于每个区域，校准要在相应区域的操作范围内施加的初始DC偏移补偿，其它区域的操作范围被限制为 阈值操作范围，以及基于所述基本DC偏移补偿，确定在所述操作范围内对所述接收装置施加的DC偏移补偿。